Sampled Data Converter Clock Switching Without Audio Artifacts

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Solution Overview

Problem

Switching between clock signals in sampled data converters for personal audio devices leads to signal artifacts such as audible 'pops' and 'clicks', which are undesirable in audio applications.

Innovation Solution

A system utilizing a digitally-controlled oscillator and a control circuit to generate an output clock signal, calculate and filter error signals, and switch between different modes of operation without artifacts, by freezing and adjusting filter outputs during mode transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If clock signals are switched between low-power and high-power modes in sampled data converters, then power consumption and performance requirements are optimized, but signal artifacts such as audible pops and clicks are introduced

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal artifacts
Core Design Contradiction:
Use of energy by moving objectVSObject-generated harmful factors

Solution Approach 1:

The system performs preliminary actions by freezing the filter output and adjusting the digitally-controlled oscillator before the actual clock switch occurs. This preparatory sequence ensures that the correction signal is already optimized to prevent artifacts, rather than reacting after the switch. The control circuit freezes the filter output at a predetermined value and adjusts the VCO tuning voltage in advance, so when the clock source switches, no audible pops or clicks occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary control mechanism between the clock switching action and the sampled data converter. The control circuit acts as a mediator that manages the transition by freezing filter outputs and adjusting the digitally-controlled oscillator. This intermediary layer smooths the transition between clock modes, preventing direct artifact generation while maintaining the power consumption benefits of clock switching.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If clock switching is implemented to meet varying performance requirements, then adaptability is improved, but device complexity increases due to additional control circuits

Engineering Contradiction:
Improveperformance adaptabilityVSAvoidcontrol circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The control circuit is designed with multi-functionality to handle multiple tasks within a single integrated structure. It simultaneously freezes the filter output, adjusts the digitally-controlled oscillator, and manages the clock switching sequence. This universal approach reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while maintaining high adaptability for different performance requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple control functions into a single integrated control circuit. The circuit combines the filter output freezing function, the digitally-controlled oscillator adjustment, and the clock switching management into one unified structure. This merging reduces the overall device complexity compared to having separate circuits for each function, while still providing the adaptability needed for varying performance requirements.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11316523B1Minimizing artifacts resulting from clock switching of sampled data converters
Publication Date: 2022.04.26 CIRRUS LOGIC INC
  • US11316523B1 patent drawing
  • US11316523B1 patent drawing
  • US11316523B1 patent drawing

AI summary

A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.