Deadlock-Free Digital Clock Switching Circuit
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Solution Overview
Problem
Conventional digital clock switching circuits for integrated circuits can enter a deadlock state when attempting to switch from one clock source to another, especially if the target clock source is not present, leading to system failure without diagnostic information.
Innovation Solution
A digital clock switching circuit utilizing two finite state machines connected to monitor each other, with a counter mechanism to verify the presence of the secondary clock source before switching, preventing deadlock by initializing a counter that decrements if the secondary clock is not verified, and re-enabling the primary clock if the counter reaches zero, indicating an error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional clock switching circuit is used to enable flexible clock source selection, then adaptability is improved, but the system can enter a deadlock state when the target clock source is not present, worsening reliability
Solution Approach 1:
The circuit performs preliminary verification of the target clock source presence before completing the switch. The secondary FSM checks whether the target clock is present and stable before enabling it, preventing deadlock by ensuring the target clock is ready in advance.
Solution Approach 2:
The circuit implements feedback mechanisms where FSMs monitor each other's clock enable signals and states. This feedback allows the system to detect the presence/absence of clock sources and adjust the switching behavior accordingly, preventing deadlock conditions.
2Reliability
If the clock switching circuit monitors the other clock enable signal to prevent glitches, then clock switching safety is improved, but the monitoring mechanism can cause deadlock when the target clock is absent, worsening system responsiveness
Solution Approach 1:
The circuit introduces an intermediary verification mechanism through the second double latch synchronizer and the secondary FSM. This intermediary layer checks clock presence independently before allowing the main switching logic to proceed, enabling safe monitoring without causing deadlock.
Solution Approach 2:
The clock switching function is segmented into independent FSMs that operate semi-autonomously. Each FSM manages its own clock enable signal and can detect errors independently, allowing the system to recover from failures in one clock domain without affecting the other.
3Measurement precision
If double latch synchronizers are used to synchronize signals from other clock domains, then signal synchronization accuracy is improved, but the circuit complexity increases, worsening device complexity
Solution Approach 1:
The double latch synchronizers are designed to serve multiple functions: they synchronize signals from other clock domains, provide error detection capability, and enable the FSMs to monitor each other's states. This multi-functionality reduces the need for additional dedicated components.
4Reliability
If the system pauses the first clock signal before allowing the second clock to take over, then glitch-free switching is achieved, but the switching time increases, worsening productivity
Solution Approach 1:
The system performs preliminary verification of the second clock's presence and stability before pausing the first clock. This ensures that the transition can occur quickly without requiring extended pause periods, as the readiness of the target clock is confirmed in advance.
Data Source
AI summary
A digital clock switching circuit and method is disclosed and is operable to deadlock-free switch a digital clock source for an integrated circuit. The circuit includes a first finite state machine associated with a first clock source and a second finite state machine associated with a second clock source. The finite state machines are connected to each other and monitor the current state of the other finite state machine. Each finite state machine receives an input select signal to control which clock source should be active and passed to a clock output. Each finite state machine includes a counter, wherein the counter associated with the active clock source is initialized to a first predetermined value when the input select signal indicates a switching off of the active clock source. The finite state machine associated with the active clock source enters a CHECK state and varies a count at each clock cycle. If the other finite state machine verifies a presence of its clock source before the counter reaches a second predetermined value the switch of the active clock source is effected.