Clock Signal Switching With Scaling for Consistent Timestamps
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Solution Overview
Problem
In data processing systems with multiple clock domains, maintaining a consistent count timestamp across different clock frequencies is challenging, especially when transitioning between low power and high performance modes, as existing solutions require complex procedures to load timestamps correctly.
Innovation Solution
A clock signal control circuitry that includes a clock selector, counter, and control logic to inhibit the output of the current clock signal during scaling value changes, allowing for seamless transitions between candidate clock signals while ensuring accurate timestamp representation by using scaling values that vary inversely with clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate counters are used for each clock domain to maintain consistent timestamps, then timestamp consistency is improved, but device complexity increases due to convoluted procedures required to load timestamps between clock domains
Solution Approach 1:
The system segments the clocking function by separating the clock signal selection from the counting function. A single counter is used across clock domains, but the clock signal fed to it is selected and scaled appropriately, dividing the problem of timestamp consistency into clock selection and counting stages
Solution Approach 2:
A clock selector acts as an intermediary between multiple candidate clock signals and the counter. This intermediary selects the appropriate clock signal and applies scaling values to ensure the counter receives properly conditioned clock pulses regardless of the source clock frequency, simplifying the overall procedure
2Speed
If clock signal frequency is increased for higher performance mode, then processing speed is improved, but maintaining timestamp consistency becomes more difficult due to frequency changes
Solution Approach 1:
The system changes parameters (clock frequency and scaling value) dynamically based on operating mode. When switching between low power and high performance modes, the clock selector changes both the clock frequency and the corresponding scaling value to maintain consistent timestamp generation despite frequency variations
Solution Approach 2:
The clock selector and scaling mechanism are designed to be dynamic, automatically adjusting the clock signal parameters and scaling values in response to mode changes. This dynamic adaptation allows the system to maintain timestamp consistency whether operating in low power or high performance mode
3Measurement precision
If scaling value is changed during clock signal transition, then timestamp accuracy is improved, but counting errors occur if clock signal is not inhibited during scaling value change
Solution Approach 1:
The system performs preliminary inhibition of the clock signal before changing the scaling value during a clock signal change operation. This preliminary action prevents the counter from operating with mismatched clock and scaling parameters, ensuring timestamp accuracy while maintaining counting reliability
Solution Approach 2:
The clock selector preliminarily prevents (inhibits) the clock signal from reaching the counter during the critical period when the scaling value is being changed. This anti-action counteracts potential counting errors by ensuring the counter only operates when clock and scaling parameters are properly synchronized
Data Source
AI summary
Clock signal control circuitry comprises a clock selector to output a current clock signal selected from two or more candidate clock signals and to execute a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal; a counter to generate a count value by counting clock pulses of the current clock signal multiplied by a scaling value; and control logic to execute a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation; in which the clock selector and the control logic are configured to cooperate to inhibit the output of the current clock signal during a scaling value change operation.