Clock Switching Circuit With Digital Filtering for Glitch-Free Transitions
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Solution Overview
Problem
Existing clock signal switching technologies in micro-controllers face issues with spurious impulses (glitches) during frequency changes and require external high-frequency oscillators or suffer from long switch delays or interruptions when the oscillator stops.
Innovation Solution
A clock generator circuit with a logic circuit and controller that uses a digital filter to eliminate glitches by timing the filter signal across the edges of the previous and new clock signals, and automatically switches to a low-frequency internal source if the external source fails, without needing a high-frequency auxiliary oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer circuit switches between asynchronous clock signals at different frequencies, then clock signal source switching is achieved, but spurious impulses (glitches) are generated on the outgoing clock signal
Solution Approach 1:
The circuit detects the last edge of the first clock signal before the switch instant and the first edge of the second clock signal after the switch instant, then generates a filter signal in advance to cover the switching interval. This preliminary action prevents glitches from occurring in the first place by pre-establishing the filtering mechanism before the actual switch happens.
Solution Approach 2:
A digital filter is introduced as an intermediary element between the multiplexer output and the CPU input. This filter acts as a mediator that processes the clock signal transitions, allowing the multiplexer to switch freely while the filter cleans up any resulting glitches before the signal reaches the CPU.
2Ease of operation
If known circuits use external clock signals for switch control, then clock signal switching is managed, but operation is interrupted when the external signal stops
Solution Approach 1:
The circuit uses its own internal clock signals (detecting edges from the actual clock signals being switched) rather than relying on external control signals. This self-service approach ensures that the switching control mechanism remains operational as long as the clock signals themselves are present, eliminating the single point of failure represented by external control signals.
3Object-generated harmful factors
If other solutions are implemented to avoid glitches, then spurious impulses are reduced, but switch delay increases
Solution Approach 1:
By detecting edges and generating the filter signal based on actual clock signal transitions rather than waiting for external control signals, the circuit performs the filtering preparation in advance of the actual switching need, minimizing any potential delay while ensuring glitches are eliminated.
4Ease of operation
If a high frequency oscillator is incorporated into the device to manage clock signal switching, then switching control is improved, but device complexity and power consumption increase
Solution Approach 1:
The circuit uses the existing clock signals themselves (CK1, CK2, etc.) as the basis for edge detection and filter signal generation, rather than requiring a separate high-frequency oscillator. This self-service approach leverages the resources already present in the system, eliminating the need for additional oscillator hardware and reducing overall device complexity.
5Ease of operation
If a high frequency oscillator is incorporated to manage clock signal switching, then switching control is improved, but power consumption increases
Solution Approach 1:
The circuit derives all control signals and filter timing from the existing clock signals themselves, eliminating the need to power a separate high-frequency oscillator. This self-service mechanism significantly reduces power consumption by utilizing already-powered signals rather than adding new power-consuming components.
Data Source
AI summary
An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.