Clock Switching Circuit With Synchronized Enable Gating
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Solution Overview
Problem
Conventional clock switching circuits generate glitch signals when switching between clock signals of different voltage levels, leading to synchronization failures and potential system failures.
Innovation Solution
A clock switching circuit comprising a clock switching control device, multiplexer, clock gate control units, and synchronization devices that generate and synchronize enable signals to ensure stable output clock signals, preventing glitches by controlling the switching process through feedback enable signals and a reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional multiplexer is used to switch between clock signals with different voltage levels, then clock switching functionality is achieved, but glitch signals are generated causing synchronization failure
Solution Approach 1:
The patent applies preliminary action by generating enable signals (en_a, en_b) before the actual clock switching occurs. These enable signals are synchronized with the reference clock and prepared in advance to control the clock gate units, ensuring that clock signals are enabled or disabled at the correct timing moments to prevent glitches during voltage level transitions
Solution Approach 2:
The patent implements feedback by using synchronized enable signals that are generated based on the reference clock and fed back to control the clock gate units. The synchronization devices ensure that the enable signals are aligned with the reference clock phase, creating a feedback mechanism that maintains proper timing relationships and prevents synchronization failure
2Speed
If clock switching is performed without synchronization control, then switching speed is improved, but pulse signals (glitches) are generated
Solution Approach 1:
The patent introduces enable signals (en_a, en_b) as intermediary control signals between the multiplexer switching and the actual clock signal transmission. These enable signals act as mediators that smoothly control the clock gate units during transitions, preventing direct voltage level conflicts that cause glitches while maintaining efficient switching speed
Solution Approach 2:
The enable signals are generated and synchronized in advance before the clock switching occurs. By preparing the enable signals with proper timing alignment to the reference clock, the system ensures that clock signals are enabled or disabled at the correct moments, preventing pulse generation during transitions
Data Source
AI summary
A glitch-free clock switching circuit receives a first clock signal and a second clock signal and outputs a third clock signal corresponding to the first clock signal or a fourth clock signal corresponding to the second clock signal according to a clock switching signal. The glitch-free clock switching circuit switches to output clock signals by stopping output of a clock signal, and then waiting for a predetermined period of time before outputting another clock signal.