Dual Clock Sub-Circuit Switching for Stable Frequency Up-Conversion
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Solution Overview
Problem
Bitcoin mining devices face instability due to sudden changes in clock frequency during the up-conversion process, leading to potential damage to circuits as a result of intermediate frequencies caused by differing stability times of sub-circuits in the clock sub-circuit.
Innovation Solution
A method and clock circuit design that employs a switching mechanism between two clock sub-circuits to smoothly transition from a first frequency to a second frequency, using a second clock sub-circuit to output the new frequency and then switch back to the first sub-circuit, thereby avoiding intermediate frequencies and maintaining chip stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a single clock sub-circuit is configured to incrementally up-convert frequency, then the chip temperature rises gradually avoiding thermal damage, but intermediate frequencies appear due to different stability times of sub-circuits causing sudden frequency changes and chip instability
Solution Approach 1:
The system divides the clock frequency up-conversion process into multiple independent clock sub-circuits, each responsible for a specific frequency range. This segmentation allows each sub-circuit to stabilize independently before transitioning to the next frequency range, eliminating intermediate frequency instability while maintaining gradual thermal increase.
Solution Approach 2:
Before switching from one clock sub-circuit to another during frequency up-conversion, the target sub-circuit is pre-configured and allowed to stabilize in advance. This preliminary action ensures that when the switch occurs, both the outgoing and incoming sub-circuits are stable, preventing sudden frequency changes and maintaining chip reliability.
2Productivity
If the clock sub-circuit is constantly configured during frequency increment, then the desired frequency is achieved, but abnormal intermediate frequencies appear before stable clock signal output causing sudden frequency changes
Solution Approach 1:
The frequency up-conversion process is segmented into discrete stages, each handled by a dedicated clock sub-circuit. This prevents the need for constant reconfiguration of a single sub-circuit, as each segment is configured once and then stabilized before transitioning to the next segment, eliminating intermediate frequency abnormalities.
Solution Approach 2:
A frequency switching controller acts as an intermediary between multiple clock sub-circuits, managing the transition process. This controller ensures that frequency increments occur only when stability conditions are met, preventing abnormal intermediate frequencies while maintaining efficient up-conversion speed.
3Reliability
If multiple clock sub-circuits are used for frequency up-conversion, then intermediate frequencies are avoided and stability is improved, but device complexity increases
Solution Approach 1:
Multiple clock sub-circuits are designed with identical functional structures, each capable of operating across the full frequency range. This universality allows the system to achieve high reliability through redundancy while minimizing complexity by using standardized, interchangeable modules rather than specialized circuits for each frequency range.
Solution Approach 2:
The system uses copies of the same clock sub-circuit design rather than entirely different circuits for each frequency range. This copying approach maintains reliability through multiple stable sources while controlling complexity by reusing proven, standardized circuit designs that can be easily replicated and managed.
Data Source
AI summary
The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.