Clock Switching Circuit for Glitch-Free Frequency Changes
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Solution Overview
Problem
Existing clock generation circuits face challenges in switching between output clock frequencies, often resulting in glitches or short pulses due to the need for low area and low power solutions that maintain consistent high and low times during frequency changes.
Innovation Solution
A clock generation circuit with a logic gate that, upon receiving control signals, switches the output clock from one input clock to another while maintaining a fixed logic state, ensuring all high and low times of the output clock are substantially equal to or greater than the lesser durations of the input clocks, thus preventing glitches during frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock generation circuit switches between different input clocks to change output frequency, then the output clock frequency is programmable, but glitches or short pulses are generated during switching
Solution Approach 1:
The circuit performs preliminary actions by setting up the second input clock and monitoring its logic state before switching occurs. The control circuit prepares the switching mechanism in advance, ensuring that when the switch is triggered, the output clock can seamlessly transition without glitches by having the second input clock ready and synchronized to the same logic state as the output clock at the moment of switching.
Solution Approach 2:
The control circuit acts as an intermediary between the first and second input clocks. It monitors the logic states of both input clocks and the output clock, and intelligently determines the optimal switching moment when all three are at the same logic state. This intermediary control mechanism ensures smooth transitions without generating glitches or short pulses during frequency changes.
2Reliability
If the circuit ensures all high and low times of output clock are equal to or greater than the lesser durations of input clocks, then glitches are prevented, but the circuit complexity increases
Solution Approach 1:
The circuit employs self-service mechanisms where the control circuit automatically monitors the logic states of input clocks and autonomously determines switching moments without external intervention. The circuit serves itself by internally tracking the duration requirements and ensuring output clock high and low times meet the specified constraints, eliminating the need for complex external control mechanisms.
Solution Approach 2:
The circuit dynamically changes parameters by adjusting the switching moment based on the logic states of the input clocks. By monitoring when input clocks are at the same logic state as the output clock, the circuit adaptively modifies its operation to maintain consistent output clock durations. This parameter-based control ensures glitch-free operation while keeping the circuit design relatively simple.
Data Source
AI summary
A clock generation circuit is disclosed. The clock generation circuit includes a logic gate configured to, in response to a control input receiving a first control signal, generate an output clock based on a first input clock received by a first identified clock input. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on a fixed logic level. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on the second input clock.