Clock Switching Circuit for Glitch-Free Frequency Changes
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Solution Overview
Problem
Existing electronic devices face stability issues due to glitches formed when switching clock signals between different frequencies, affecting system performance.
Innovation Solution
A switching circuit comprising a detection circuit, inverters, determination circuits, D-type flip-flops, and a clock gating circuit, which detects enable signals to switch between clock signals without glitches, and optionally includes a synchronization circuit to handle asynchronous clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock signals are switched between different frequencies, then the electronic device can adapt to different application scenarios, but glitches are formed in clock signals affecting system stability
Solution Approach 1:
The detection circuit proactively monitors the enable signals before switching occurs, and the synchronization circuit prepares the switching control signal in advance to ensure proper timing. This preliminary detection and preparation prevents glitches by ensuring the switching happens at the correct moment when both clock domains are properly aligned, thus maintaining system stability while enabling frequency adaptation.
2Device complexity
If a simple clock switching mechanism is used, then the device complexity is reduced, but glitches occur during clock signal switching
Solution Approach 1:
The synchronization circuit acts as an intermediary between the first and second clock domains. It receives enable signals from both domains, detects their relative timing, and generates a switching control signal that coordinates the clock switching. This intermediary component ensures proper synchronization without requiring complex switching logic, thus maintaining reliability while keeping the overall device complexity manageable.
3Speed
If clock switching is performed without synchronization, then the switching speed is improved, but metastable states are generated affecting system reliability
Solution Approach 1:
The synchronization circuit performs preliminary timing detection by monitoring enable signals from both clock domains before the actual switching occurs. This preliminary action identifies the optimal switching moment when both domains are properly aligned, allowing fast switching without metastable states. The key is that this detection happens in advance, so the actual switching can be executed quickly without compromising reliability.
Data Source
AI summary
A switching circuit coupled to a first oscillator circuit and a second oscillator is provided. The first oscillator circuit generates a first clock signal according to a first enable signal. The second oscillator generates a second clock signal according to a second enable signal. The switching circuit uses the first or second clock signal as an output clock according to a detection signal. The switching circuit includes a first D-type flip-flop and a second D-type flip-flop. The first D-type flip-flop includes a first reset terminal receiving the first enable signal. The second D-type flip-flop includes a second reset terminal receiving the second enable signal.