Clock Signal Switching Circuit for Glitch-Free Selection
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Solution Overview
Problem
Current digital circuits face challenges in minimizing glitches during clock signal selection, which is energy and chip surface area intensive.
Innovation Solution
A circuit configuration that includes a selector for choosing a clock signal, a switch to control the output, and a method where the application of a control signal sequentially turns off the switch, selects the signal, and then turns it back on, incorporating delays to manage signal transitions and prevent glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switch is used to select between multiple clock signals, then clock signal selection is enabled, but glitches are generated during the transition and power consumption increases
Solution Approach 1:
The patent applies preliminary action by turning off the switch before the clock signal transition occurs and keeping it off until after the transition is complete. The control circuit detects the transition state and maintains the switch in the off state during the critical transition period, preventing glitches from propagating. This sequential operation (turn off → wait for transition → turn on) ensures that the switch only conducts when the clock signal is stable, eliminating glitch generation while maintaining clock signal selection capability.
2Adaptability or versatility
If a switch is used to select between multiple clock signals, then clock signal selection is enabled, but power consumption increases
Solution Approach 1:
The patent implements periodic action by controlling the switch to operate in a periodic manner: off during normal operation, turned on only briefly after clock signal transitions, and off again during the next transition period. The control circuit monitors clock signal transitions and activates the switch only when necessary (after transitions), creating a periodic on-off pattern rather than continuous operation. This reduces average power consumption while maintaining the ability to select different clock signals when needed.
3Object-generated harmful factors
If delays are added to manage signal transitions, then glitches are filtered out, but signal propagation time increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a control circuit that acts as a mediator between the clock signal source and the switch. The control circuit detects clock signal transitions and generates control signals to manage the switch timing, inserting only the minimum necessary delays (configured to be at least two clock cycles) around transition points. This intermediary control mechanism filters glitches by timing the switch to be off during transitions, while keeping delays minimal and localized only to transition periods rather than continuous operation.
Data Source
AI summary
The present disclosure provides a circuit for supplying a clock signal. An example circuit for supplying a clock signal comprises a selector of one signal out of a plurality of clock signals; a switch between the selector and a node for outputting the selected clock signal, the circuit being configured so that the application of a control signal for selecting one of the clock signals causes, in the order, the turning off of the switch, the selection of the signal via the selector, and the turning on of the switch.