Clock Switching Circuit for Glitch-Free Frequency Transitions
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Solution Overview
Problem
Existing clock generation circuits face issues with glitches or short pulses when switching between output clocks of different frequencies, particularly in low area and low power configurations.
Innovation Solution
A clock generation circuit design that utilizes a sequence of flip-flops and logic gates to synchronize the transition between input clocks, ensuring the output clock maintains consistent high and low durations during frequency changes, thereby eliminating glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock frequency is changed in programmable clock generation circuits, then output clock frequency is adjusted, but glitches or short pulses are generated during transition
Solution Approach 1:
The circuit performs preliminary actions by pre-loading the next clock phase data into shift registers before the actual clock switch occurs. The control logic prepares the transition by sequentially shifting in the new clock phase information in advance, so that when the switch is executed, the new clock is already ready to be output without glitches.
Solution Approach 2:
The clock switching process is segmented into multiple discrete phases using shift registers and control logic. Instead of a direct switch, the circuit divides the transition into sequential steps where each shift register stage holds and transfers clock phase information in a controlled manner, allowing the system to move from one clock phase to another through intermediate states rather than a single abrupt change.
2Use of energy by stationary object
If low area and low power configurations are used in clock generation circuits, then circuit size and power consumption are reduced, but glitch-free switching becomes more difficult to achieve
Solution Approach 1:
The control logic automatically manages the clock switching process without requiring external intervention or complex control mechanisms. The shift registers and control logic work together in a self-contained manner, where the control signal automatically triggers the sequential loading and switching process, eliminating the need for additional control circuitry that would increase power consumption and area.
Solution Approach 2:
The circuit changes the phase parameter of the clock signal in a controlled sequential manner through the shift registers. By changing the clock phase in discrete steps rather than directly, the circuit achieves glitch-free switching while maintaining simple logic that consumes minimal power and occupies small area.
3Device complexity
If simple clock switching logic is used, then device complexity is reduced, but glitch generation during frequency transitions increases
Solution Approach 1:
The shift registers act as intermediary elements between the input clock signals and the output clock. Instead of directly switching between clock sources, the intermediary shift registers buffer and sequentially transfer the clock phase information, mediating the transition in a way that prevents direct conflicts and glitch generation while keeping the overall logic relatively simple.
Data Source
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AI summary
A clock generation circuit is disclosed. The clock generation circuit includes a logic gate configured to, in response to a control input receiving a first control signal, generate an output clock based on a first input clock received by a first identified clock input. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on a fixed logic level. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on the second input clock.