Two-Way Clock Switching with Edge-Synchronized Glitch Prevention
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Solution Overview
Problem
Existing clock switching systems in electronic devices often experience glitches when switching between clock signals, particularly due to asynchronous RESET pulses and synchronization issues, which can lead to undefined initial states and errors during power-up.
Innovation Solution
A clock switch system utilizing a control stage with feedback from the multiplexer control signal and clock selection signal to manage tristate buffers, ensuring synchronized switching and preventing glitches by using logical AND operations and delayed tristate buffers with regenerative loops to maintain signal integrity during transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional clock switch uses a multiplexer with asynchronous select signal for switching between clock signals, then the switching operation is simple and fast, but clock glitches occur in the output signal when switching coincides with clock edges
Solution Approach 1:
The patent applies preliminary action by synchronizing the multiplexer control signal to the clock edge before switching occurs. The synchronization step ensures that the control signal is aligned with the clock signal timing, preventing glitches by ensuring switching happens at appropriate moments relative to clock edges, thus maintaining signal integrity while enabling fast switching.
2Reliability
If a clock switch uses synchronous switching with clock edges to avoid glitches, then signal integrity is maintained, but the system requires a well-defined RESET pulse and cannot handle asynchronous power-up properly
Solution Approach 1:
The patent applies self-service by making the tristate buffers automatically synchronize their enable signals to the respective clock edges. This self-synchronization mechanism eliminates the need for external RESET pulses or complex power-up sequencing, as the buffers naturally align their operation with clock edges during power-up, simplifying operation while maintaining signal integrity.
3Productivity
If tristate buffers are switched into high impedance mode asynchronously, then the clock switch operation is simple and fast, but undefined initial states and errors occur during power-up
Solution Approach 1:
The patent applies feedback by using the clock signal itself to control the timing of tristate buffer enablement. The buffer enable signals are derived from and synchronized to their respective clock edges, creating a feedback mechanism that ensures buffers are always enabled at appropriate moments. This eliminates undefined initial states during power-up while maintaining efficient asynchronous switching operation.
Data Source
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AI summary
The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer (MUX) receives the tristate buffer outputs and selects one clock signal in response to a multiplexer control signal (MUX_SEL). A control stage (CONTROL) received a clock selection signal (SEL) and provides multiplexer control signal (MUX_SEL). A change in multiplexer control signal (MUX_SEL) is triggered by a next edge of target clock (CLK1) following a delay. This prevents glitches in the output signal.