Clock Switching Circuit with Fixed-State Glitch Suppression
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Solution Overview
Problem
Clock generation circuits face challenges in switching between output clock frequencies, often resulting in glitches or short pulses due to the need for low area and low power solutions that maintain consistent high and low times during frequency changes.
Innovation Solution
A clock generation circuit with a logic gate that receives control signals to switch between input clocks, ensuring all high and low times of the output clock are substantially equal to or greater than the lesser durations of the input clocks, preventing glitches by maintaining a fixed logic state during the transition period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock generation circuit switches between different input clocks to change output frequency, then the output clock frequency is programmable, but glitches or short pulses are generated during the transition
Solution Approach 1:
The circuit performs preliminary actions by setting up the second input clock and control signals before the switching event occurs. The second input clock is enabled and synchronized in advance, and control signals are prepared to ensure the transition happens only when both clocks are in compatible states, preventing glitches during frequency switching
Solution Approach 2:
The circuit introduces intermediary control signals and logic gates that mediate the transition between different input clocks. These control signals act as intermediaries to coordinate the switching process, ensuring that the output clock maintains continuous valid transitions without glitches by controlling when each input clock is passed to the output
2Reliability
If the circuit ensures all high and low times of output clock are equal to or greater than the lesser durations of input clocks, then glitch prevention is achieved, but the circuit complexity increases
Solution Approach 1:
The circuit segments the clock switching function into distinct components: multiple input clock paths, individual control signals for each clock, and logic gate structures that independently manage each clock's contribution to the output. This segmentation allows the circuit to maintain consistent clock durations through coordinated control of separate clock paths rather than requiring a monolithic complex structure
Solution Approach 2:
The circuit employs dynamic control signals that adaptively manage the switching between input clocks based on their respective high and low time characteristics. The control signals dynamically enable or disable specific input clocks during different phases of the output clock cycle, ensuring that the output maintains minimum duration requirements without requiring static complex circuitry
Data Source
AI summary
A clock generation circuit is disclosed. The clock generation circuit includes a logic gate configured to, in response to a control input receiving a first control signal, generate an output clock based on a first input clock received by a first identified clock input. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on a fixed logic level. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on the second input clock.