Clock Synthesizer Hitless Reference Switching With Frequency Offset Tracking
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Solution Overview
Problem
Existing clock synthesizers experience frequency drift and phase glitches during switching between reference clocks, which is unacceptable in applications requiring a stable clock source with constant frequency.
Innovation Solution
A clock synthesizer architecture that employs two phase locked loops, a controlled oscillator, a switch, and a frequency tracker to store and gradually attenuate frequency offsets, ensuring hitless reference switching with stable output frequency and phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If hitless reference switching is implemented to prevent phase glitches, then phase stability is improved, but frequency drift occurs as the output clock gradually drifts to the new reference frequency
Solution Approach 1:
The frequency tracker stores the frequency offset between reference clocks in advance before switching occurs. When switching happens, this pre-stored offset information is immediately applied to the controlled oscillator, preventing frequency drift rather than allowing gradual drift as in conventional systems.
Solution Approach 2:
The frequency tracker acts as an intermediary component that captures and holds frequency offset information between the reference clocks and the controlled oscillator. This intermediary stores the offset and provides it to the adder, which then compensates the controlled oscillator to maintain stable output frequency during reference switching.
2Device complexity
If conventional DPLL switching is used between reference clocks, then simplicity is maintained, but phase glitches and frequency jumps occur during switching
Solution Approach 1:
The frequency tracker serves as an intermediary that captures frequency offset information and provides it to the adder, which then compensates the controlled oscillator. This intermediary mechanism prevents phase glitches and frequency jumps during reference clock switching while maintaining relative system simplicity.
Solution Approach 2:
The system uses feedback from the frequency tracker to monitor and store offset information, which is then fed back to the adder and controlled oscillator to maintain stable output frequency and phase during switching operations.
3Speed
If the output clock locks directly to the new reference clock frequency, then fast locking is achieved, but frequency offset causes unacceptable frequency change
Solution Approach 1:
The frequency tracker stores the frequency offset in advance before switching occurs. When the output clock switches to the new reference clock, this pre-stored offset is immediately applied to compensate for frequency changes, allowing fast locking while maintaining frequency stability.
Solution Approach 2:
The system applies preliminary compensation using the stored frequency offset to counteract the frequency drift that would normally occur when locking to a new reference clock. This preliminary anti-action prevents the harmful frequency change before it can affect the output.
Data Source
AI summary
A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.