Clock Switching Controller for Glitch-Free PCIe Speed Transitions
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Solution Overview
Problem
In computer systems, existing technologies face challenges in seamlessly switching clock speeds for multiple links running at different speeds without interrupting data transfers, particularly in PCIe protocols, where compatibility with older generations requires glitch-free updates within a specific timeframe.
Innovation Solution
A device comprising a frequency divider and a clock switching controller generates multiple clock signals and determines the maximum data rate requested by ports, providing a transmit clock signal and clock enabling signals to match each port's requirements, ensuring glitch-free switching within a known timeframe.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single PLL is used to generate clock signals for multiple links, then area and power are saved, but glitch-free switching between different clock speeds becomes difficult to achieve
Solution Approach 1:
The system performs preliminary actions by generating all required clock signals (250 MHz, 500 MHz, 1 GHz) in advance using a single PLL and frequency dividers, then selectively enables the appropriate clock signal before switching is needed. This allows seamless transitions between different PCIe generation modes without interrupting data transfers, as the required clock signals are already prepared and ready for immediate activation.
Solution Approach 2:
Frequency dividers are introduced as intermediary components between the single PLL output and the multiple link requirements. These dividers create intermediate clock signals at different frequencies (250 MHz, 500 MHz, 1 GHz) from the PLL output, enabling a single PLL to serve multiple links at different speeds without direct connection to each link, thus achieving both power savings and reliable switching.
2Adaptability or versatility
If clock speed is switched to match different port requirements, then compatibility with various PCIe generations is improved, but data transfer interruption may occur during switching
Solution Approach 1:
The system prepares all possible clock signals (250 MHz for PCIe 1.x, 500 MHz for PCIe 2.0, 1 GHz for PCIe 3.0) in advance using frequency dividers before any switching is required. When a port needs to change its clock speed to match a different PCIe generation, the desired clock signal is already available and can be enabled immediately without interruption to data transfers on other ports.
Solution Approach 2:
The clock enabling signals are segmented and independently controlled for each port, allowing individual ports to switch between different clock speeds (250 MHz, 500 MHz, 1 GHz) based on their specific PCIe generation requirements while other ports continue operating at their current speeds without being affected, thus maintaining data transfer continuity.
3Reliability
If multiple PLLs are used per PCIe IP core to support multiple links at different speeds, then each link can operate independently, but area and power consumption increase
Solution Approach 1:
Multiple PLLs that would traditionally be used to generate clock signals for multiple links are merged into a single PLL. Frequency dividers are then used to create the required clock signals (250 MHz, 500 MHz, 1 GHz) from this single PLL output, allowing multiple links to operate independently at different speeds while consuming less power than multiple separate PLLs would require.
Solution Approach 2:
A single PLL is designed to perform multiple functions by generating clock signals at different frequencies (250 MHz, 500 MHz, 1 GHz) that can be distributed to multiple PCIe links. This universal clock generation approach eliminates the need for dedicated PLLs for each link, reducing both area and power consumption while maintaining independent operation capability for each link.
4Adaptability or versatility
If clock switching is performed within four clock cycles, then compatibility with PCIe specification is maintained, but switching complexity increases
Solution Approach 1:
All required clock signals are generated in advance using frequency dividers, and clock enabling signals are prepared for each port. This preliminary preparation allows the system to comply with the PCIe specification requirement of switching within four clock cycles without complex switching logic, as the switching simply involves enabling the pre-prepared clock signal that is already available.
Data Source
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AI summary
A device configured to switch a clock speed for multiple links running at different clock speeds. The device comprises: a frequency divider configured to generate from a source clock signal a plurality of clock signals at different frequencies; a clock switching controller configured to select one of the clock signals for a plurality of ports and output the selected clock signal to each port at a data rate requested by each port; and wherein the clock switching controller is configured to select one of the clock signals that matches a maximum data rate among data rates requested by the plurality of ports.