Clock Switching Algorithm for Multi-Standard Radio Synchronization
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Solution Overview
Problem
Existing clock synchronization solutions in shared baseband deployments face challenges in maintaining synchronization and switching between primary and secondary clock sources, particularly when the input synchronization reference is lost, leading to unsynchronized outputs and impaired network performance.
Innovation Solution
A method and apparatus that recover a clock from one system's output to regenerate a synchronization source for the other system, ensuring consistent timing even when the input synchronization source is lost, and aligning secondary and primary clocks based on quality factors to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock synchronization solutions are used in shared baseband deployments, then each system operates with independent synchronization inputs, but the outputs become unsynchronized when one or both systems lose their synchronization inputs
Solution Approach 1:
The patent introduces a shared clock source as an intermediary between the first and second systems. This shared clock source receives synchronization inputs and distributes synchronized clock signals to both systems, ensuring they remain synchronized even when individual systems lose their own synchronization inputs. The shared clock source acts as a mediator that coordinates timing between heterogeneous systems.
Solution Approach 2:
The patent merges the clock synchronization function into a single shared clock source that serves both systems. Instead of each system maintaining independent clock synchronization, the clock sources are combined into a shared resource that provides unified timing, ensuring synchronization between systems while reducing overall complexity.
2Reliability
If the system switches to a single clock source when synchronization is achieved, then synchronization is maintained, but the system must handle complex switching logic between primary and secondary clocks
Solution Approach 1:
The patent implements dynamic clock source selection where the shared clock source can automatically switch between primary and secondary synchronization inputs based on their availability and quality. This dynamic behavior allows the system to maintain synchronization stability while the switching logic is encapsulated within the shared clock source, simplifying operation for the broader system.
Solution Approach 2:
The shared clock source incorporates feedback mechanisms to monitor the status of primary and secondary synchronization inputs. Based on this feedback, the system automatically determines when to switch between clock sources, ensuring synchronization stability without requiring complex manual switching logic. The feedback loop continuously assesses clock source quality and makes appropriate switching decisions.
3Adaptability or versatility
If heterogeneous systems with independent synchronization inputs are used, then system independence is maintained, but holdover requirements vary and lead to unsynchronized outputs
Solution Approach 1:
The shared clock source is designed as a universal synchronization component that can accept multiple types of synchronization inputs and serve multiple heterogeneous systems with different holdover requirements. This multi-functional approach maintains system independence while providing unified timing precision, as the shared clock source adapts to serve various system types through a common interface.
Data Source
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AI summary
A radio system having multi-standard mixed mode radios is described. The mixed mode radios are used to support combining of digital baseband from a first and a second radio equipment controller. A primary clock associated with the first radio equipment controller and a secondary clock associated with the second radio equipment controller is provided. The quality of the primary clock is evaluated and the primary clock is referenced to the first radio equipment controller if the clock is determined to have appropriate quality factors. The quality of the secondary clock is then evaluated and the secondary clock is referenced to the second radio equipment controller if the secondary clock is determined to have appropriate quality factors. The second radio equipment controller is then referenced to the primary clock once the primary and secondary clocks are aligned.