Clock Switching Stability Detection for Glitch-Free Wake-Up
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Solution Overview
Problem
Mobile communication devices face inefficiencies in low-power operations due to premature switching of reference clocks, leading to metastability and reduced effectiveness in power conservation.
Innovation Solution
An oscillation detection logic is used to determine the stability of a higher-frequency reference clock before switching, ensuring glitch-free transitions by deriving a sampled clock signal and comparing it against a lower-frequency reference clock, thus preventing premature switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the reference clock is switched off or reduced in frequency during low-power operations, then power consumption is reduced, but the electronic circuit cannot become operational quickly when exiting low-power mode
Solution Approach 1:
The oscillation detection logic is activated before the reference clock is fully ramped up to detect early signs of instability. This preliminary detection allows the system to wait for proper stabilization before switching, avoiding premature operations that would cause metastability while still enabling quick exit from low-power mode.
Solution Approach 2:
The system implements feedback through the oscillation detection logic that continuously monitors the reference clock signal. When the clock signal stabilizes and meets frequency criteria, the detection logic provides feedback to authorize the switch, ensuring the clock is stable before the electronic circuit becomes operational.
2Loss of time
If the electronic circuit switches to the reference clock before it is stable, then the circuit can exit low-power mode faster, but metastability occurs in the electronic circuit
Solution Approach 1:
The oscillation detection logic performs preliminary detection of clock stability before the electronic circuit is allowed to switch. By detecting frequency characteristics in advance, the system ensures the clock is stable before enabling the circuit, preventing metastability while minimizing delay.
Solution Approach 2:
The oscillation detection logic acts as an intermediary between the reference clock and the electronic circuit. It monitors the clock signal and only permits the circuit to switch when the clock meets stability criteria, thereby preventing direct switching to unstable clocks that would cause metastability.
3Reliability
If the reference clock is ramped up fully before switching, then stability is ensured, but the effectiveness of low-power operations is reduced
Solution Approach 1:
The oscillation detection logic performs preliminary stability checks during the clock ramp-up process rather than waiting for full stabilization. This allows the system to detect when the clock is sufficiently stable to switch, maintaining reliability while preserving the effectiveness of low-power operations by avoiding excessive waiting time.
Solution Approach 2:
The system uses partial action by detecting clock stability at a threshold level rather than requiring full ramp-up completion. The oscillation detection logic identifies when the clock reaches sufficient stability for operation, allowing switching before the clock reaches its maximum stable state, thus balancing reliability with power efficiency.
Data Source
AI summary
Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.