Clock Synchronization Messaging With NIC Control Dependencies

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing clock synchronization methods in networks face challenges in detecting synchronization failures quickly and maintaining precise clock error bounds, leading to potential data corruption and uncertainty, especially in data centers with distributed databases.

Innovation Solution

Implementing a software-based synchronous messaging scheme using work queue entries and control dependencies, such as semaphores, to conditionally send clock synchronization messages, ensuring timely detection and propagation of synchronization failures without hardware restrictions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional asynchronous PTP messaging is used, then device complexity is reduced, but synchronization failure detection is delayed and clock error bounds cannot be maintained

Engineering Contradiction:
Improvesynchronization failure detectionVSAvoidmessaging scheme complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by having the boundary clock send synchronization messages to followers immediately upon receiving a valid synchronization message from the leader, before any failure can occur. This proactive approach ensures that if the leader fails, the boundary clock will detect the failure quickly (when no message is received) and propagate this failure information downstream, maintaining tight clock error bounds. The work queue mechanism with control dependencies enables this timely failure propagation without requiring complex hardware modifications.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If synchronous messaging with tight error bounds is implemented, then clock synchronization reliability is improved, but hardware design complexity increases

Engineering Contradiction:
Improveclock error boundsVSAvoidhardware design
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex hardware-based synchronous messaging mechanisms with a software-based implementation using work queues and control dependencies. Instead of requiring hardware-level synchronization primitives or dedicated synchronization circuits, the invention uses standard software constructs (work queue entries, semaphores, and control dependency mechanisms) to achieve synchronous messaging behavior. This substitution maintains tight clock error bounds while significantly reducing hardware design complexity, allowing existing network interface controllers to be used without specialized synchronization hardware.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If hardware-based synchronous messaging is used, then synchronization precision is improved, but adaptability to software-based systems is reduced

Engineering Contradiction:
Improvesynchronization precisionVSAvoidsoftware implementation flexibility
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent achieves universality by designing a software-based synchronization mechanism that can be implemented on standard network interface controllers without requiring specialized hardware. The work queue entry mechanism with control dependencies is a software construct that can run on general-purpose processors, making the system adaptable to various hardware platforms. This approach maintains synchronization precision comparable to hardware-based solutions while providing the flexibility and adaptability of software-based systems, allowing the same mechanism to work across different hardware architectures and vendor implementations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12476775B2Synchronous clock synchronization messaging
Publication Date: 2025.11.18 MELLANOX TECHNOLOGIES LTD(IL)
  • US12476775B2 patent drawing
  • US12476775B2 patent drawing
  • US12476775B2 patent drawing

AI summary

In one embodiment, a system includes a network interface controller to receive a first clock-synchronization message from a clock-synchronization leader device and send a second clock-synchronization messages to at least one clock-synchronization follower device, and a processor to execute software to generate the second clock-synchronization message, and generate a control dependency to condition sending the second clock-synchronization message by the network interface controller to the at least one clock-synchronization follower device on the network interface controller receiving the first clock-synchronization message from the clock-synchronization leader device.