Communication Circuit Clock Synchronization via Amplifier Control Signals

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Solution Overview

Problem

Existing communication devices lack a dedicated timing output mechanism, making it difficult to synchronize their local reference clocks and derive a timing reference effectively.

Innovation Solution

A method and system for synchronizing two devices with integrated communication circuits by using control outputs from the circuits to determine relative timings of events and synchronize external clocks, utilizing external amplifiers for signal transmission and reception, and employing a synchronisation circuit to adjust clock phases based on these timings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If communication devices use internal reference clocks for timing operations, then timing accuracy is improved, but the ability to externally access and synchronize these clocks is limited when no dedicated clock output mechanism is provided

Engineering Contradiction:
Improvetiming accuracyVSAvoidexternal clock access
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent uses control outputs from the communication circuit as intermediary signals to derive timing information about internal clock events without directly exposing the clock itself. These control outputs indicate when external amplifiers should be active, which correlates with internal clock timing, thereby mediating between the internal clock system and external synchronization needs

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces direct electrical access to the internal clock (mechanical/electrical system) with indirect timing derivation through control output signals. Instead of tapping into the clock signal directly, the system uses control outputs that reflect clock timing to infer and synchronize external clocks

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If devices synchronize clocks using dedicated timing outputs, then synchronization accuracy is improved, but device compatibility is reduced when some devices lack such outputs

Engineering Contradiction:
Improvesynchronization accuracyVSAvoiddevice compatibility
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent makes the control outputs serve multiple functions: their primary function is to control external amplifiers, but they also serve as timing reference signals for synchronization. This multi-functionality allows devices without dedicated clock outputs to still provide timing information through their existing control outputs, improving compatibility while maintaining synchronization capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If devices expose internal clock states externally, then timing reference derivation is simplified, but hardware complexity increases when hardware design does not allow external exposure

Engineering Contradiction:
Improvetiming reference derivationVSAvoidhardware complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent leverages the existing control output signals that the communication circuit already generates for amplifier control. Instead of adding new hardware to expose clock states, the system uses the self-generated control outputs that already contain timing information, allowing the device to serve its own timing reference needs without additional hardware complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3831132B1Time synchronisation
Publication Date: 2025.12.03 MOTION APPLIED LIMITED
  • EP3831132B1 patent drawingFigure 1~2
  • EP3831132B1 patent drawingFigure 3~4

AI summary

A device comprising: a wireless communication interface, the communication interface being capable of using an external signal processing device to support a transmission or reception communication event and being configured to provide a first output signal from the communication interface for disabling such a signal processing device after the communication event; a clock external to the communication interface; and a synchronisation circuit configured to receive the first output signal and to synchronise the clock in dependence on the timing of the first output signal.