Clock Synchronization Control for Delay Variation and Frequency Drift
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Solution Overview
Problem
Existing frequency synchronization methods in data transfer networks are susceptible to disturbances from transfer delay variations, particularly in technologies like ADSL and GPON, and are slow to respond to changes such as temperature fluctuations, making them inadequate for modern network requirements.
Innovation Solution
A method and device that form phase-error and frequency-error indicators to achieve phase-locking and frequency-locking between reference and controlled clock signals, with the ability to monitor deviations and replace the frequency-controlled clock signal with a phase-controlled clock signal based on detected changes in circumstances like temperature, to improve synchronization quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase synchronization is used to achieve timing synchronization between network elements, then phase-locking between reference clock signal and phase-controlled clock signal is achieved, but the system becomes susceptible to disturbances caused by transfer delay variation
Solution Approach 1:
The patent divides the clock signal control into two independent parts: phase control and frequency control. Phase-controlled and frequency-controlled clock signals are generated separately, each optimized for its specific function, rather than using a single phase-controlled signal for both purposes.
Solution Approach 2:
The patent changes the control parameters by introducing a long update interval for frequency control (e.g., 1 second or longer) compared to phase control. This parameter change allows the frequency-controlled clock signal to be less sensitive to short-term transfer delay variations while maintaining accurate frequency synchronization.
2Reliability
If frequency synchronization with long update interval is used to reduce transfer delay variation effects, then frequency-locking is achieved with reduced sensitivity to delay variation, but the system becomes slow to respond to changes in temperature and local circumstances
Solution Approach 1:
The patent implements dynamic switching between phase-controlled and frequency-controlled clock signals based on monitored deviation. When the deviation exceeds a threshold, the system dynamically adjusts by replacing the frequency-controlled signal with the phase-controlled signal, enabling adaptive response to changing conditions.
Solution Approach 2:
The patent introduces feedback mechanisms to monitor the deviation between phase-controlled and frequency-controlled clock signals in real-time. This feedback enables the system to detect when environmental changes affect synchronization accuracy and trigger appropriate corrective actions.
3Reliability
If monitoring and dynamic replacement of clock signals is implemented, then resilience to transfer delay variation and environmental changes is improved, but device complexity increases
Solution Approach 1:
The patent prepares both phase-controlled and frequency-controlled clock signals in advance, maintaining them as ready-to-use alternatives. This preliminary preparation allows rapid switching between signals when needed, without requiring complex real-time generation or adjustment mechanisms.
Data Source
AI summary
A device for controlling frequency synchronization includes a processor for controlling a phase-controlled clock signal to achieve phase-locking with a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking with the reference clock signal. The processor is also configured to monitor a deviation between the frequency and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with, or on the basis of, the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.