Clock Synchronization Circuit With Delay Skip for Phase Instability
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Solution Overview
Problem
The accuracy and speed of semiconductor synchronization circuits are compromised by phase unstable periods during clock signal synchronization, particularly at higher frequencies, due to the limitations in delay time tuning operations.
Innovation Solution
A synchronization circuit that includes a variable delay circuit, phase detector, and delay control circuit capable of detecting phase unstable periods and performing a delay skip operation to adjust delay control signals, thereby skipping the unstable period during tuning, utilizing both coarse and fine delay lines for precise timing adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If delay time tuning operation is performed at higher clock signal frequencies, then synchronization speed is improved, but phase instability occurs causing accuracy degradation
Solution Approach 1:
The patent implements a delay skip operation that detects phase unstable periods and skips over them during delay time tuning. When phase instability is detected in a current delay period, the circuit advances to a next delay period, bypassing the unstable region. This allows the synchronization circuit to maintain high-speed operation while avoiding accuracy degradation by not dwelling in unstable phase regions.
2Productivity
If delay time tuning operation is performed at higher clock signal frequencies, then tuning speed is improved, but phase unstable periods increase causing reliability degradation
Solution Approach 1:
The patent employs a feedback mechanism where the phase detector continuously monitors phase differences and provides feedback to the delay control circuit. This feedback enables real-time detection of phase unstable periods, allowing the system to adaptively adjust the delay tuning process by skipping unstable periods and maintaining reliable synchronization even at high clock frequencies.
3Measurement precision
If phase unstable periods are skipped during delay time tuning, then accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the delay time tuning process into discrete delay periods with identifiable boundaries. By dividing the continuous delay adjustment into segmented stages, the circuit can detect phase instability at each segment boundary and make discrete skip decisions. This segmentation approach enables accurate phase detection and skip operations without requiring overly complex continuous analysis circuitry.
Data Source
AI summary
A synchronization circuit may include: a variable delay circuit configured to delay a first clock signal by a varied delay time according to delay control signals, and configured to output a delayed signal of the variable delay circuit as a second clock signal; a phase detector configured to generate a phase detection signal by detecting a phase difference between the first and second clock signals; and a delay control circuit configured to perform a phase unstable period detection operation according to the phase detection signal, and configured to perform a delay skip operation to adjust the delay control signals such that a phase unstable period, detected in the phase unstable period detection operation, is skipped in a delay time tuning operation.