Clock Synchronization Circuit Using Delayed Signal Comparison
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Solution Overview
Problem
Current methods for synchronizing devices, such as in wireless media systems or time-sensitive communication systems, face challenges due to clock drift caused by environmental factors, leading to power consumption issues and slow stabilization times in clock updates.
Innovation Solution
A circuit and method that estimate time differences between clocks using a series of delay signal lines and comparison units to determine the closest matching delayed time marker, allowing for efficient synchronization with minimal power consumption and quick stabilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If continuous monitoring of time difference is performed using software to update clock sources, then synchronisation accuracy is improved, but power consumption increases and stabilization time increases
Solution Approach 1:
The patent implements periodic monitoring instead of continuous monitoring by using delay units to create multiple delayed versions of time markers and comparing them at specific intervals. The processor only needs to perform comparisons when events occur, rather than continuously monitoring, thereby reducing power consumption while maintaining synchronisation accuracy.
Solution Approach 2:
The patent pre-generates multiple delayed versions of time markers using delay units before comparison is needed. This preliminary action allows the system to quickly determine time differences without requiring continuous processing, reducing both power consumption and stabilization time when clock updates are performed.
2Measurement precision
If continuous monitoring of time difference is performed using software to update clock sources, then synchronisation accuracy is improved, but processor power consumption increases
Solution Approach 1:
The patent replaces software-based continuous monitoring with a hardware-based comparison circuit that uses delay units and comparison units. This hardware implementation performs time difference measurements automatically without requiring continuous processor intervention, significantly reducing processor power consumption while maintaining measurement precision.
3Measurement precision
If clock sources are updated frequently to maintain synchronisation, then synchronisation accuracy is improved, but stabilization time increases
Solution Approach 1:
The patent pre-computes multiple delayed versions of time markers using delay units before they are needed for comparison. This preliminary preparation allows the system to quickly switch between different time marker versions when clock updates are required, minimizing stabilization time while maintaining synchronisation accuracy.
Data Source
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AI summary
A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.