Clock Synchronization Circuit Using Fewer Transceiver Terminals
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Solution Overview
Problem
The increasing number of signals transmitted and received between transmitter and receiver devices leads to a proliferation of wirings and semiconductor chip terminals, hindering the miniaturization of transmitter devices.
Innovation Solution
A transmission device with an oscillator for oscillating a first clock signal and a control signal reception unit to receive control signals from an external device, and a reception device with a signal generation unit to generate control signals based on a comparison of reference and second clock signals, allowing for reduced wiring and terminal count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock signals are transmitted between transmitter and receiver, then clock synchronization is improved, but the number of wirings and terminals increases
Solution Approach 1:
The patent merges the transmission of multiple clock signals (first clock signal and second clock signal) into a single wiring by encoding them as differential signals. The transmitter generates both clock signals and transmits them through one differential wiring pair, while the receiver extracts both signals from this single transmission channel, thereby reducing the total number of wirings and terminals required
Solution Approach 2:
The differential wiring structure serves multiple functions simultaneously: it transmits both the first clock signal and the second clock signal, provides impedance matching, and enables clock synchronization without requiring separate dedicated wirings for each clock signal. This multi-functionality reduces the overall terminal count on the semiconductor chip
2Adaptability or versatility
If the number of terminals on semiconductor chip increases, then more functions can be integrated, but miniaturization becomes difficult
Solution Approach 1:
The invention combines multiple clock signal transmission functions into a single differential wiring interface, reducing the number of terminals required on the semiconductor chip. By transmitting both first and second clock signals through one differential pair rather than requiring separate wirings for each, the chip terminal count is reduced, enabling miniaturization while maintaining full functionality
Solution Approach 2:
The patent transitions from a single-ended signaling approach to differential signaling, utilizing both polarities of the differential pair to convey clock information. This dimensional change in signal representation allows two clock signals to be transmitted through what would traditionally be considered a single wiring channel, effectively reducing terminal requirements
Data Source
AI summary
An objective of the present technology is to provide a transmission device, a reception device, and a transceiver system of which miniaturization can be achieved. The transmission device includes an oscillator configured to oscillate a first clock signal; and a register signal reception unit configured to receive a register signal transmitted from a reception device and used for controlling the first clock signal. The reception device includes a signal generation unit configured to generate a register signal for controlling a first clock signal transmitted from the transmission device based on a comparison result obtained by comparing a reference clock signal with one of the first clock signal and a second clock signal which is based on the first clock signal; and a register signal transmission unit configured to transmit the register signal generated by the signal generation unit to the transmission device.