Clock Synchronization Circuit With Stepped Frequency Locking
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Solution Overview
Problem
Existing clock synchronization devices face challenges in quickly synchronizing a clock signal with a data signal during asynchronous transmission while consuming minimal energy, especially when the frequency of the clock signal is close to the data signal frequency, leading to slow synchronization and potential phase shifts.
Innovation Solution
A clock synchronizing circuit comprising a first flip-flop for detecting edges of the data signal, a phase comparator with delayed flip-flops and an AND gate to adjust the clock signal frequency based on phase differences, and a second circuit to modify the clock signal frequency, allowing for efficient synchronization with adjustable delay between 2% and 50% of the data rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock signal frequency is adjusted to match the data signal frequency during asynchronous transmission, then synchronization accuracy is improved, but synchronization time increases and energy consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple fixed frequency steps in the clock signal generator before synchronization is needed. When synchronization is required, the system can quickly select and switch to the appropriate pre-configured frequency step that matches the data signal frequency, rather than gradually adjusting from an unknown frequency. This reduces synchronization time while maintaining accuracy.
Solution Approach 2:
The patent implements dynamics by making the clock signal frequency adjustable through a controllable frequency adjustment circuit. The system dynamically switches between multiple fixed frequency steps based on detection results, allowing rapid adaptation to different data signal frequencies without continuous gradual adjustment, thus reducing both synchronization time and energy consumption.
2Measurement precision
If the clock signal frequency is adjusted to match the data signal frequency during asynchronous transmission, then synchronization accuracy is improved, but energy consumption increases
Solution Approach 1:
The system pre-configures multiple fixed frequency steps in advance, so when synchronization is needed, it can quickly select the matching frequency without continuous adjustment. This reduces the time the frequency adjustment circuit remains active, thereby reducing energy consumption while maintaining synchronization accuracy.
Solution Approach 2:
The patent employs periodic action by using discrete frequency steps rather than continuous frequency adjustment. The frequency adjustment occurs in periodic steps, allowing the system to reach the target frequency faster and spend less time in the adjustment state, thus reducing overall energy consumption while achieving accurate synchronization.
3Adaptability or versatility
If continuous frequency adjustment is used to synchronize clock and data signals, then adaptability to different frequencies is improved, but system complexity increases
Solution Approach 1:
The patent implements dynamics by using a controllable frequency adjustment circuit that can switch between multiple fixed frequency steps. This provides adaptability to different data signal frequencies while avoiding the complexity of continuous frequency adjustment mechanisms, as the system only needs to select from pre-defined frequency options.
Solution Approach 2:
The system changes the frequency parameter in discrete steps rather than continuously. By preparing multiple fixed frequency steps in advance and switching between them based on detection results, the system achieves frequency adaptability with simpler control logic and fewer components compared to continuous frequency adjustment systems.
Data Source
AI summary
In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.