Clock Synchronization in Heterogeneous Multi-Layer Communication Systems
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Solution Overview
Problem
Current communication systems face challenges in maintaining stable clock synchronization between higher layers in multi-clock systems, especially when heterogeneous clocks are used, leading to errors and system failures due to variable delay times and differing synchronization methods across lower layers.
Innovation Solution
A method for clock synchronization between higher layers using synchronization information from lower layers, involving the transmission of information between protocol adaptation layers (PALs) and media access control/physical (MAC/PHY) layers, with synchronization signals and clock adjustments to maintain stable synchronization even with variable delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet transmission through multiple lower layers is performed, then data communication between higher layers is enabled, but variable delay times are inserted causing synchronization errors to accumulate
Solution Approach 1:
The patent introduces a timing synchronization intermediary mechanism where the receiving terminal PAL measures the actual packet reception time and compares it with the packet generation time information. This intermediary timing measurement process identifies delay variations introduced by lower layers and enables clock adjustment to compensate for these delays, thus maintaining synchronization stability while allowing efficient data communication through multiple layers.
Solution Approach 2:
The patent implements a feedback mechanism where the receiving terminal PAL continuously monitors packet reception timing, calculates delay times, and uses this feedback information to adjust its clock. The feedback loop compares expected timing with actual reception timing, identifies synchronization deviations caused by variable delays in lower layers, and applies corrective clock adjustments to maintain stable synchronization despite ongoing data communication.
2Reliability
If clock synchronization is performed using packet time information through lower layers, then higher layer clock synchronization is achieved, but synchronization errors grow over time causing unstable clocks
Solution Approach 1:
The patent implements a feedback mechanism where the receiving terminal PAL continuously monitors packet reception timing, calculates delay times, and uses this feedback information to adjust its clock. The feedback loop compares expected timing with actual reception timing, identifies synchronization deviations caused by variable delays in lower layers, and applies corrective clock adjustments to maintain stable synchronization despite ongoing data communication.
Solution Approach 2:
The patent applies partial correction by adjusting the clock only for the specific delay amount measured from packet timing information, rather than attempting to correct all possible sources of timing variation. This partial action approach focuses on compensating for the identifiable delay components introduced by lower layer packet transmission, achieving sufficient clock stability without over-correcting for un controllable timing variations.
3Measurement precision
If large amounts of data are used for clock information to correct accumulative errors, then synchronization accuracy is improved, but data efficiency is reduced
Solution Approach 1:
The patent extracts only the essential timing information needed for synchronization from the packet data, specifically the packet generation time information and actual reception time. Instead of using large amounts of data for clock correction, the invention extracts and utilizes only the critical timing parameters, achieving sufficient synchronization accuracy while maintaining high data efficiency by transmitting and processing minimal synchronization data.
4Adaptability or versatility
If heterogeneous clocks are used in higher and lower layers, then protocol flexibility is improved, but clock synchronization between higher layers becomes difficult
Solution Approach 1:
The patent introduces a timing synchronization intermediary mechanism where the receiving terminal PAL measures the actual packet reception time and compares it with the packet generation time information. This intermediary timing measurement process identifies delay variations introduced by lower layers and enables clock adjustment to compensate for these delays, thus maintaining synchronization stability while allowing efficient data communication through multiple layers.
Solution Approach 2:
The patent implements a universal synchronization mechanism based on packet timing information that can accommodate heterogeneous clocks in both higher and lower layers. The timing measurement and comparison process works independently of the specific clock frequencies used in different layers, providing a universal approach that maintains synchronization reliability across diverse protocol configurations with different clock sources.
Data Source
AI summary
A method for clock synchronization between higher layers using synchronization information provided from lower layers in multi-clock communication system in which the higher layers and the lower layers use heterogeneous clocks is provided.