Clock Synchronization Hysteresis State Switching

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Solution Overview

Problem

In telecommunication networks, clock synchronization is hindered by noise-induced state toggling between free running and locked modes, particularly due to high Packet Delay Variation (PDV), leading to frequent disconnections of radio base stations and disruptions in network traffic.

Innovation Solution

A network node with a synchronization control module and a Kalman filter estimates time and frequency errors, using adaptive thresholds to manage synchronization states and reduce state toggling by implementing a hysteresis mechanism that adapts to actual PDV, ensuring stable clock synchronization and minimizing out-of-service times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single threshold is used to determine synchronization state, then the decision rule is simple, but noise causes frequent state toggling between free running and locked modes

Engineering Contradiction:

Improvesynchronization state decision ruleVSAvoidsynchronization state stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent applies dynamics by making the threshold adaptive rather than fixed. The threshold automatically adjusts based on the measured time difference between client and reference clocks. When the time difference is small (good synchronization), the threshold is lowered to maintain locked state. When the time difference is large (poor synchronization), the threshold is raised to allow transition to free running state. This dynamic threshold adaptation prevents noise-induced toggling while maintaining simple decision logic.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of the threshold value based on synchronization quality. Instead of using a constant threshold, the system modifies the threshold parameter dynamically according to the measured time difference. This parameter change allows the system to adapt to varying noise conditions and synchronization states, preventing frequent toggling while keeping the decision rule relatively simple.

Inventive Principle:

Principle #35Parameter changes

2Loss of time

If the clock synchronization threshold is lowered to reduce out-of-service time, then traffic handling starts earlier, but noise causes false synchronization declarations and state toggling

Engineering Contradiction:

Improveout-of-service timeVSAvoidsynchronization accuracy

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The dynamic threshold adapts to the current synchronization quality, allowing the system to use a lower effective threshold when synchronization is good (reducing out-of-service time) while maintaining higher reliability when noise is present. The threshold automatically rises when time difference increases, preventing false synchronization declarations.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system uses feedback from continuous time difference measurements to adjust the threshold. The measured time difference between client and reference clocks feeds back into the threshold calculation, creating a closed-loop system that automatically adjusts sensitivity based on actual synchronization quality, thereby reducing false positives while minimizing out-of-service time.

Inventive Principle:

Principle #23Feedback

3Adaptability or versatility

If packet switching networks are used for synchronization signal transmission, then network flexibility is improved, but Packet Delay Variation introduces high noise causing state toggling

Engineering Contradiction:

Improvenetwork configuration flexibilityVSAvoidPacket Delay Variation noise

Core Design Contradiction:

Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of PDV noise into a beneficial adaptation mechanism. Instead of trying to eliminate PDV or use a different network type, the system uses the measured time difference (which includes PDV effects) to dynamically adjust the threshold. This transforms the noise problem into an adaptive parameter adjustment that automatically compensates for PDV variations.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The system changes the threshold parameter based on the actual synchronization measurements that include PDV effects. By adapting the threshold to the measured time difference, the system accommodates PDV variations without requiring changes to the network infrastructure, maintaining flexibility while reducing noise-induced toggling.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10244497B2Clock synchronization with hysteresis state switching

Publication Date: 2019.03.26 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

AI summary

The invention refers to synchronizing a client clock of a network node to a reference clock, wherein the network node performs the steps of receiving from the reference clock synchronization data, determining a comparison value indicative of a degree of deviation of the client clock with respect to the reference clock, and determining a synchronization state (S1, S2) out of a free running state (S1) and a locked state (S2), based on the comparison value, a first threshold (TH1), and a second threshold (TH2). The invention further refers to a telecommunication node (21) and a computer program.