Clock Synchronization Controller Using Integral and Fractional Modifiers
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Solution Overview
Problem
Current methods for synchronizing devices, such as those in wireless media systems, face challenges due to clock drift caused by environmental factors, leading to out-of-sync playback and inefficiencies in power consumption from continuous monitoring and stabilization processes.
Innovation Solution
A controller system that modifies clock signals using a combination of integral and fractional clock signal modifiers to synchronize clocks by adjusting clock pulses or delays, allowing for efficient synchronization without continuous re-tuning, thereby reducing power consumption and maintaining synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software continuously monitors time difference and updates clock source, then synchronization accuracy is maintained, but power consumption increases and stabilization time is required
Solution Approach 1:
The patent implements periodic monitoring of time differences between clocks rather than continuous monitoring. The controller checks time markers at specific intervals, determines time differences, and updates clock sources periodically. This approach maintains synchronization accuracy while allowing the processor to enter low-power states between monitoring cycles, significantly reducing power consumption compared to continuous software-based monitoring.
2Reliability
If clock source is updated continuously, then synchronization accuracy is maintained, but additional stabilization time is required
Solution Approach 1:
The patent applies preliminary adjustments to clock sources based on predicted time differences rather than waiting for drift to accumulate. By monitoring time markers and calculating anticipated drift, the controller proactively adjusts clock sources before significant desynchronization occurs. This prevents the need for frequent large-scale updates that would require stabilization time, as the system maintains clocks within acceptable tolerances through proactive rather than reactive adjustment.
3Use of energy by moving object
If hardware-based clock modification is used, then power consumption is reduced and synchronization is maintained, but device complexity increases
Solution Approach 1:
The patent introduces a controller as an intermediary component that coordinates between time marker generators, time difference determiners, and clock source update mechanisms. This controller acts as a central coordinator that receives time markers from different clocks, calculates time differences, and directs appropriate clock source updates. While this adds a control layer, it organizes the synchronization process efficiently, allowing hardware-based modifications to be managed systematically rather than through complex distributed logic across multiple components.
Data Source
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AI summary
A controller for modifying a clock signal from a first clock, the controller comprising: a time comparison unit configured to estimate a time difference between a first signal associated with the first clock and a reference signal received at the controller, wherein the time comparison unit is configured to determine if the time difference is greater than or less than one clock period of the first clock; a first signal modifier configured to modify the clock signal by an integer number of clock periods; and a second signal modifier configured to modify the clock signal by a fraction of the clock period, wherein the controller is configured to select, for modifying the clock signal, the first signal modifier if the time difference is greater than one clock period or the second signal modifier if the time difference is less than one clock period.