Clock Synchronization Circuit for Power Noise Jitter Reduction
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in curbing clock signal jitter caused by power supply noise, which affects the performance of systems by introducing fluctuations in the clock signal, and existing solutions are complex and may delay device startup.
Innovation Solution
A semiconductor integrated circuit design that includes a phase synchronization circuit, edge detection circuit, clock division circuit, and delay adjuster to generate a synchronized clock signal, detect edges, and adjust delays to displace the timing of the clock signal, thereby reducing power supply noise-induced jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the clock supply circuit shares the power supply with other elements, then the device structure is simplified, but power supply noise increases causing clock signal jitter
Solution Approach 1:
The patent segments the power supply system by introducing a dedicated power supply line for the clock supply circuit, separating it from the common power supply used by other elements. This segmentation isolates the clock circuit from power supply noise generated by other elements, resolving the contradiction between simplified structure and clock signal stability.
2Reliability
If phase adjustment circuits are added to reduce jitter, then clock signal stability improves, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by adjusting the phase of the clock signal in advance before it is distributed to other elements. The phase adjustment circuit pre-compensates for potential jitter issues, ensuring stable clock signals without requiring complex real-time correction mechanisms, thus improving reliability while controlling complexity.
3Reliability
If delay adjustment is applied to displace power supply noise timing, then clock signal jitter is reduced, but the device startup time increases
Solution Approach 1:
The patent changes the timing parameter of the clock signal by introducing a delay adjustment mechanism that displaces the timing of power supply noise generation. This parameter change allows the system to operate in an optimal timing window where noise does not affect clock signal stability, resolving the contradiction between reliability and startup time by optimizing the operational parameters rather than adding complex control logic.
Data Source
AI summary
A semiconductor integrated circuit includes: a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal; an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.