Clock Synchronization via Kalman Filter Estimation
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Solution Overview
Problem
Existing clock synchronization methods, such as Precision Time Protocol (PTP), face challenges in networks with non-IEEE 1588 aware devices, leading to significant packet delay variation and requiring feedback from slave to master nodes, while also being sensitive to the quality of local clocks and transportation media.
Innovation Solution
A system comprising a master device with a clock module, counter module, packet generation module, and communication module, and a slave device with packet monitoring, clock frequency estimation, and frequency offset calculation modules, which transmit and receive synchronization packets to synchronize clock frequencies without requiring feedback, using a Kalman filter algorithm to estimate the master clock frequency and adjust the slave clock accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PTP is used for clock synchronization in networks with non-IEEE 1588 aware devices, then clock synchronization can be achieved, but packet delay variation becomes significant and feedback mechanisms are required
Solution Approach 1:
The patent extracts the clock synchronization information from complex PTP feedback mechanisms and encapsulates it in simple synchronization packets that can be processed by non-IEEE 1588 aware devices. The master device generates synchronization packets containing timestamp information, which slave devices can process without requiring sophisticated PTP implementation or feedback capabilities.
Solution Approach 2:
The patent creates simplified copies of clock synchronization information in the form of synchronization packets with timestamps. Instead of requiring devices to implement complex PTP protocols, the system distributes timestamp copies that slave devices can use to adjust their clocks using simple local algorithms, eliminating the need for complex feedback mechanisms.
2Adaptability or versatility
If PTP is implemented with non-IEEE 1588 aware devices, then network coverage is extended, but synchronization performance deteriorates due to packet delay variation
Solution Approach 1:
The patent segments the clock synchronization function into two parts: (1) the master device generates synchronization packets with precise timestamps using IEEE 1588, and (2) slave devices independently calculate their clock adjustments using local algorithms. This segmentation allows non-IEEE 1588 aware devices to participate in synchronization without requiring sophisticated PTP implementation, maintaining both compatibility and precision.
Solution Approach 2:
The synchronization packet acts as an intermediary carrier that transports precise timestamp information from the master device to slave devices. These packets serve as a simplified mediator that non-IEEE 1588 aware devices can process, bridging the gap between high-precision time sources and simple network devices without requiring complex protocol implementation at the slave end.
3Measurement precision
If feedback mechanisms are used in PTP for slave-to-master communication, then clock accuracy is improved, but network dependency and complexity increase
Solution Approach 1:
The patent enables slave devices to perform self-service clock synchronization by using simple local algorithms to process incoming synchronization packets and adjust their clocks autonomously. Instead of requiring complex slave-to-master feedback mechanisms, each slave device independently calculates its clock offset and applies corrections locally, maintaining clock accuracy while eliminating sophisticated feedback requirements.
Solution Approach 2:
The patent inverts the traditional PTP feedback approach by having the master device send unidirectional synchronization information without requiring feedback. Instead of slave devices communicating clock status back to the master, the system uses the master's timestamps as the sole reference, with slave devices autonomously adjusting their clocks based on received packet timing information.
Data Source
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AI summary
According to some embodiments, a master device sends synchronization packets to one or more slave devices, and does so periodically based on a master clock signal having a master clock frequency. At each of the slave devices, an algorithm estimates the master clock frequency based on the timing of synchronization packet arrivals the slave device. The algorithm may estimate the master clock frequency using both the currently-observed timing of synchronization packet arrivals and the history of previous synchronization packet arrivals (e.g., previously-observed timing of synchronization packet arrivals). Based on the estimated master clock frequency, each of the one or more slave devices can update the frequency of their respective slave clock signal (e.g., using a frequency offset) to match that of the estimated master clock frequency.