Clock Synchronization via Local Time Base and Phase-Locked Loop
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Solution Overview
Problem
Existing computer systems face increased power consumption and processing overhead due to the need for sample-rate conversion when synchronizing clock signals between components connected via interfaces, particularly across different clock domains.
Innovation Solution
A system that uses a local time base in a second component to generate and maintain a local clock signal that tracks a reference clock signal from a first component, and adjusts the local clock signal to remove clock drift during intermittent data transmission, employing a numerically controlled oscillator (NCO) with a microelectromechanical systems (MEMS) oscillator and frequency synthesizer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sample-rate conversion is performed to synchronize clock signals between components, then synchronization accuracy is improved, but processing overhead and power consumption increase
Solution Approach 1:
The patent extracts the clock synchronization function from the data processing path and implements it independently through a dedicated time base and phase-locked loop circuit. This separates the synchronization task from the main data processing, reducing the computational burden on the CPU and associated power consumption while maintaining accurate clock synchronization between components.
Solution Approach 2:
The patent introduces an intermediary time base circuit that includes a phase-locked loop and local oscillator. This intermediary component generates and adjusts local clock signals without requiring complex sample-rate conversion processing. The intermediary circuit handles the synchronization function through hardware-based phase locking rather than software-based sampling, significantly reducing processing overhead and power consumption.
2Measurement precision
If sample-rate conversion is performed to synchronize clock signals between components, then synchronization accuracy is improved, but processing overhead increases
Solution Approach 1:
The patent extracts the clock synchronization function from the data processing path and implements it independently through a dedicated time base and phase-locked loop circuit. This separates the synchronization task from the main data processing, reducing the computational burden on the CPU and associated power consumption while maintaining accurate clock synchronization between components.
Solution Approach 2:
The patent replaces the software-based sample-rate conversion mechanism with a hardware-based phase-locked loop circuit. Instead of using complex digital signal processing algorithms to synchronize clocks, the system uses an intermediary hardware circuit that locks phases through electrical feedback, significantly reducing processing overhead and computational complexity.
3Reliability
If a local time base is used to generate and maintain clock signals during intermittent transmission, then synchronization reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by having the local time base continuously generate and maintain clock signals even when the interface is inactive. The phase-locked loop circuit continuously tracks and adjusts the local clock to match the host clock frequency, so that when transmission resumes, synchronization is already established. This proactive maintenance of timing information ensures reliable synchronization during intermittent transmission without requiring complex re-synchronization procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces computational overhead and power consumption by enabling synchronization between components without the need for sample-rate conversion, facilitating efficient clock domain crossings and maintaining synchronization even during intermittent timing information transmission.
Implementation Method 1
a phase-locked loop that locks to the host clock signal and generates the local clock signal
Implementation Method 2
The local time base is a numerically controlled oscillator (NCO) that includes a microelectromechanical systems (MEMS) oscillator and a frequency synthesizer
Data Source
AI summary
The disclosed embodiments provide a system that facilitates synchronization between a first component and a second component connected to the first component via an interface in a computer system. During an active state of the interface, the system uses a local time base in the second component to generate a local clock signal that tracks a host clock signal from the first component. Next, during an inactive state of the interface, the system uses the local time base to maintain the local clock signal at the second component. Finally, during a subsequent active state of the interface after the inactive state, the system adjusts the local clock signal to remove clock drift between the local clock signal and the host clock signal.