Clock Synchronization Circuit With Metastability-Masking TDC
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Solution Overview
Problem
Existing clock synchronization methods in digital circuits are unreliable at high operating frequencies due to metastability issues, as they rely on synchronizers that delay computations and do not guarantee success, especially when dealing with multiple clock domains.
Innovation Solution
A method and circuit for synchronizing clock pulses that translates incoming clock signal transitions into binary values representing deviation from expected arrival times, calculates phase corrections, and uses a multiplexed time-to-digital converter (TDC) with metastability-masking registers to achieve reliable synchronization without relying on metastability-free inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronizers are used to resolve metastability, then metastability resolution probability increases, but system delay increases and reliability does not improve at high frequencies
Solution Approach 1:
The patent replaces traditional mechanical/synchronous waiting-based synchronizers with an asynchronous event-driven architecture. Instead of using clocked flip-flops that require waiting for metastability resolution, the system uses asynchronous event signals that immediately propagate when conditions are met, eliminating the inherent delay of synchronous waiting while maintaining reliability through event-based validation.
Solution Approach 2:
The patent changes the fundamental operating parameter from synchronous clocked operation to asynchronous event-driven operation. By transitioning from fixed clock cycles to dynamic event signaling, the system achieves both immediate response (reducing delay) and reliable metastability handling through explicit event validation rather than probabilistic waiting.
2Productivity
If synchronizers are used at high operating frequencies, then clock synchronization is attempted, but reliability decreases due to insufficient metastability resolution time
Solution Approach 1:
The patent replaces synchronous synchronizer circuits with asynchronous event-driven logic. This substitution allows the system to operate at high frequencies without relying on metastability resolution time, as the asynchronous architecture immediately responds to events without requiring waiting periods, thereby maintaining both high productivity and reliability.
Solution Approach 2:
The patent implements preliminary validation of event signals before they are processed further in the system. By checking and validating events upfront through the asynchronous logic, the system ensures reliability is maintained even at high operating frequencies where traditional synchronizers would fail due to insufficient resolution time.
3Adaptability or versatility
If multiple clock domains are used to preserve benefits, then system versatility increases, but metastability risks increase
Solution Approach 1:
The patent extracts the metastability problem from the clock synchronization process by using asynchronous event-driven logic. Instead of trying to synchronize clocks directly (which creates metastability risks), the system extracts and processes events independently, allowing multiple clock domains to coexist without interfering with each other, thus maintaining versatility while eliminating metastability risks.
Solution Approach 2:
The patent introduces asynchronous event signals as intermediaries between different clock domains. These events act as mediators that carry information between domains without requiring direct synchronization, allowing multiple clock domains to operate independently while still achieving coordinated functionality, thereby maintaining versatility without introducing metastability risks.
4Reliability
If synchronizers are used to handle metastable inputs, then metastability is addressed, but system complexity increases
Solution Approach 1:
The patent replaces complex synchronous synchronizer circuits with simpler asynchronous event-driven logic. The asynchronous approach uses straightforward event validation and propagation mechanisms rather than complex multi-stage synchronizer circuits, achieving reliable metastability handling with reduced device complexity.
Solution Approach 2:
The patent implements self-validating event logic that automatically handles metastability without requiring external synchronizer circuits. The asynchronous event system inherently validates and processes signals through its own logic structure, eliminating the need for additional complexity from external synchronizers while maintaining reliable metastability handling.
Data Source
AI summary
The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.