Clock-Domain Synchronization Circuit for Metastability Detection
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Solution Overview
Problem
Conventional data synchronization circuits fail to synchronize data between function modules operating with asynchronous clock signals of differing frequencies, leading to metastability defects and incorrect data transmission.
Innovation Solution
A semiconductor device and method that utilize a clock delay circuit to generate delayed clock signals and synchronized retrieval circuits to retrieve input data at specific timing transitions, determining whether data has undergone metastability based on clock values, thereby ensuring synchronization without defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional synchronization circuit using two flip-flops (one for rising edge, one for falling edge) is used to synchronize data between asynchronous clock signals, then metastability defects can be eliminated for clock signals of the same frequency, but the circuit cannot handle cases where the transmission source clock frequency is higher than the synchronization clock frequency
Solution Approach 1:
The patent introduces dynamic adaptability by making the synchronization circuit's operation mode switchable based on the clock frequency relationship. The control signal generation circuit dynamically determines whether to use rising-edge-triggered or falling-edge-triggered flip-flops based on real-time detection of clock frequency relationships, enabling the circuit to adapt to different frequency scenarios rather than being fixed for a single case
Solution Approach 2:
The patent changes the operational parameters of the synchronization circuit by switching between different trigger modes (rising edge vs. falling edge) based on the clock frequency relationship. When the transmission source clock frequency is higher, the circuit switches to using falling-edge-triggered flip-flops instead of rising-edge-triggered ones, effectively changing the synchronization mechanism to match the frequency conditions
2Speed
If data is directly transmitted between function modules operating with asynchronous clock signals, then transmission speed is maintained, but metastability occurs causing incorrect data retrieval
Solution Approach 1:
The patent applies preliminary action by performing data sampling at specifically timed moments before the actual data retrieval operation. The synchronization circuit samples the input data at the appropriate edge (rising or falling) of the synchronization clock signal, ensuring that data is captured at a stable state before it is needed, thereby preventing metastability while maintaining transmission speed
Solution Approach 2:
The synchronization circuit acts as an intermediary between the transmission source and the destination function modules. It receives data from the transmission source, synchronizes it to the destination's clock domain using appropriately triggered flip-flops, and then outputs the synchronized data, mediating the asynchronous interface between different clock domains
Data Source
AI summary
A semiconductor device that receives input data synchronized with a first clock signal and generates output data synchronized with a second clock signal, includes a clock delay circuit that generates first and second delay clock signals, first and second synchronized retrieval circuits that respectively retrieve the input data at timings when each of logical values of the second clock signal and second delay clock signal being switched, to respectively obtain first and second retrieved data, and a clock value retrieval circuit that retrieves a value of the first clock signal at timings when the second clock signal and first delay clock signal respectively switch from the first logical value to the second logical value, to respectively output first and second clock values, and an output circuit that outputs, as the output data, the first or second retrieved data, depending on a value of the first and second clock values.