Clock Synchronization Using Frequency and Phase Offset Tracking

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Solution Overview

Problem

Existing clock synchronization techniques, such as Precise Time Protocol (PTP) and IEEE 802.11v, face challenges in achieving high-resolution adjustments and managing complexity across different devices and subsystems, especially in wireless environments.

Innovation Solution

A unified implementation of hardware clocks that incorporates a frequency offset acquisition and compensation (FOAC) module and a joint phase and residual frequency offset tracking (JPRFOT) module, which work together to synchronize clocks across devices and subsystems by adjusting timer signals based on frequency and phase offsets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional clock synchronization techniques (PTP, IEEE 802.11v) are used, then basic time synchronization is achieved, but high-resolution adjustments and system stability deteriorate due to frequency and phase offsets

Engineering Contradiction:
Improvetime synchronization resolutionVSAvoidsystem stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements feedback mechanisms through the FOAC module that continuously monitors frequency offsets between reference and local clocks, and the JPRFOT module that tracks phase offsets. These modules use the measured offsets to generate correction signals that are fed back to adjust the local clock, creating a closed-loop control system that maintains high-resolution synchronization while compensating for drift and instability

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes clock parameters by adjusting frequency and phase based on measured offsets. The FOAC module detects frequency deviations and the JPRFOT module detects phase deviations, then both modules work together to modify the local clock's frequency and phase parameters in real-time, enabling high-resolution adjustments that maintain synchronization accuracy while adapting to changing conditions

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If frequency and phase offset compensation is implemented, then time synchronization accuracy is improved, but device complexity increases due to additional modules

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidhardware clock system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges frequency offset acquisition and phase tracking functions into a unified hardware clock system. The FOAC module and JPRFOT module are integrated to work together, with the FOAC providing frequency correction and the JPRFOT providing phase correction, combining multiple synchronization functions into a coordinated system that achieves high accuracy without requiring completely separate independent modules for each function

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hardware clock system is designed with multi-functional modules that perform multiple roles. The FOAC module not only acquires frequency offsets but also generates correction signals, while the JPRFOT module tracks phase offsets and coordinates with FOAC for combined frequency and phase adjustment. This multi-functionality reduces the need for additional dedicated components, managing complexity while maintaining high synchronization accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12278642B2Clock synchronization
Publication Date: 2025.04.15 NXP USA INC
  • US12278642B2 patent drawing
  • US12278642B2 patent drawing
  • US12278642B2 patent drawing

AI summary

A time-synchronization apparatus and/or method involves identifying a frequency offset by implementing a frequency-offset-acquisition process which includes counting cycles of a local clock signal within a period of a reference pulse train. A phase offset of the local clock signal is determined, a residual frequency error is generated based on the phase offset, and at least one timer-adjustment signal that is based on the frequency offset and the residual frequency error is provided.