Clock Synchronization via Packet-Switched Network Modules
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Solution Overview
Problem
Existing clock synchronization methods for distributed modules in packet-switched networks either require special hardware or forgo synchronization entirely, leading to bit slip and inefficiencies in telecommunications systems.
Innovation Solution
A method where at least two modules use local clock generators to transmit synchronous clock signal packets, with one module acting as a master to synchronize the others by measuring and minimizing deviation, eliminating the need for complex hardware solutions like IEEE 1588, and utilizing standard hardware and software components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If special hardware components are used for clock synchronization (e.g., central clock generator with special clock signals), then clock synchronization accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces the mechanical/electrical special hardware clock distribution system with a software-based packet-switched network timing system. Instead of using dedicated clock signal cables and central clock generators, the invention uses standard network infrastructure to transmit timing information as data packets, thereby reducing hardware complexity while maintaining synchronization capability
Solution Approach 2:
The patent creates a virtual copy of the clock signal by encoding timing information into data packets that traverse the network. Rather than physically distributing identical clock signals through special hardware, the system transmits timing references that slave modules use to reconstruct synchronized timing, eliminating the need for complex hardware distribution networks
2Device complexity
If IEEE 1588 PTP protocol is used for software-based clock synchronization, then hardware requirements are reduced, but measurement precision deteriorates due to lack of high-precision timestamps
Solution Approach 1:
The patent enables standard network components to provide timing functionality without requiring special hardware enhancements. The system uses readily available network infrastructure and software to generate and process timing packets, allowing the network itself to serve the synchronization function without external specialized equipment
Solution Approach 2:
The patent changes the approach to timestamp generation by using software-based timing mechanisms with sufficient precision for the application requirements. Instead of demanding hardware-level precision, the system adjusts the timing parameters and measurement intervals to achieve adequate synchronization accuracy through software control of standard components
3Device complexity
If clock signals are transmitted over packet-switched networks, then hardware requirements are reduced, but synchronization accuracy deteriorates due to network jitter and delays
Solution Approach 1:
The patent implements a feedback mechanism where slave modules measure their synchronization status relative to the master module and report deviations back to the system. This feedback loop enables dynamic adjustment of timing parameters to compensate for network variations, maintaining synchronization accuracy despite packet-switched network characteristics
Solution Approach 2:
The patent performs preliminary timing measurements and calculations before actual synchronization is required. The system pre-characterizes network delays and jitter patterns, then uses this information to proactively adjust timing offsets, ensuring accurate synchronization even in the variable environment of packet-switched networks
Data Source
AI summary
A method or an arrangement for the clock synchronization of a plurality of distributed modules of an information or communication system where said modules are coupled via a packet-switched network is adapted so that at least two of said modules are controlled by a local clock generator of the modules using an adjustable frequency, and a clock signal is transmitted via the network in the form of clock signal packets. One of said at least two modules takes over the function of a master module, and all remaining modules synchronize the local clock of the modules with the clock of the master module.