Clock Synchronization Using Packet Timestamps and Software PLL

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Solution Overview

Problem

Traditional time synchronization methods across devices on a network, such as NTP, face issues with accuracy and convergence time due to network bandwidth consumption and real-world interference, resulting in poor synchronization and user experience.

Innovation Solution

The implementation of a software-implemented phase-locked loop (PLL) with a proportional-integral-derivative (PID) controller as a loop filter, which includes time data in packet headers for opportunistic transfer, reducing network overhead and enhancing synchronization accuracy and speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional NTP protocol is used for time synchronization, then network time synchronization can be achieved, but synchronization accuracy is limited to approximately 1 millisecond and convergence time is substantial

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidconvergence time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the fundamental parameters of time synchronization by using packet timestamp data from existing network traffic instead of dedicated NTP packets. This allows achieving approximately 2.5 microseconds accuracy in 2.4 seconds, dramatically improving both precision and reducing convergence time compared to traditional NTP's 1 millisecond accuracy with substantial convergence time

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a software-implemented phase-locked loop (PLL) with a proportional-integral-derivative (PID) controller as a loop filter as an intermediary mechanism. This PLL processes timestamp data from packet headers to generate adjusted timing signals, acting as a mediator between raw network timing data and synchronized device clocks, thereby achieving superior synchronization performance

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of information

If dedicated NTP packets are exchanged for time synchronization, then time data can be transferred, but network bandwidth is consumed

Engineering Contradiction:
Improvetime data transferVSAvoidnetwork bandwidth consumption
Core Design Contradiction:
Loss of informationVSLoss of energy

Solution Approach 1:

The patent merges the time synchronization function with existing network data traffic by embedding timestamp information in packet headers. Instead of separate dedicated NTP packets, the time data is combined with regular network traffic, eliminating additional bandwidth consumption while maintaining continuous time synchronization capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes existing network packets serve multiple functions: both data transmission and time synchronization. By utilizing timestamp data in packet headers for synchronization purposes, the system achieves multi-functionality where regular network traffic simultaneously performs communication and timing reference roles, reducing overall network overhead

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12095895B1System for time synchronization
Publication Date: 2024.09.17 AMAZON TECH INC
  • US12095895B1 patent drawing
  • US12095895B1 patent drawing
  • US12095895B1 patent drawing

AI summary

Maintaining time synchronization between clocks of different devices allows various operations, such as accurate timestamping input data, coordinating presentation of output, and so forth. A pairwise synchronization between a first and second device is provided by opportunistically including timing data within packets transmitted between the devices. A clock sync module in a second device uses a software-implemented phase-locked loop (PLL) with a software-implemented proportional-integral-derivative (PID) controller to synchronize a second clock in the second device to a first clock of the first device. The use of the clock sync module to process the timing data provides clock synchronization without introducing jitter or other undesirable effects at the second device. Using the clock sync module, the timing of the second clock of the second device quickly converges with the first clock. The close convergence facilitates time-sensitive operations, such as synchronizing presentation of content from many participating wireless devices.