Master-Slave Clock Synchronization for Phase-Controlled Power Dissipation
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Solution Overview
Problem
Existing timing systems lack control over time relationships between clock signals generated by different integrated electronic devices, limiting the ability to manage overall power dissipation effectively.
Innovation Solution
A timing system comprising a master device and at least one slave device, synchronized through a synchronization signal that ensures controlled phase shifts between clock signals, allowing for balanced power dissipation and enhanced power driving capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple integrated electronic devices generate clock signals independently using local oscillators, then each device can operate autonomously, but the time relationships between clock signals from different devices cannot be controlled
Solution Approach 1:
A synchronization device is introduced as an intermediary component that receives a reference clock signal and distributes synchronized clock signals to multiple integrated electronic devices. This mediator ensures precise time relationships between devices while allowing them to maintain autonomous operation through the standardized synchronization interface.
Solution Approach 2:
All integrated electronic devices are placed in an equipotential timing environment by providing them with clock signals from the same synchronization source. This ensures that all devices operate from the same time reference, eliminating timing drift and ensuring consistent time relationships across the system.
2Device complexity
If clock signals from different integrated electronic devices are not synchronized, then device complexity is reduced, but the ability to control overall power dissipation is limited
Solution Approach 1:
The synchronization device introduces periodic control signals that coordinate the operation of switching regulators across different integrated electronic devices. By synchronizing the switching cycles periodically, the system can control when power conversion occurs, preventing simultaneous operation and reducing peak power dissipation.
Solution Approach 2:
The synchronization device monitors the reference clock signal and adjusts the distributed clock signals to maintain precise time relationships. This feedback mechanism ensures that even if local oscillators drift, the synchronized devices continue to operate with controlled timing, enabling effective power dissipation management.
3Power
If switching regulators operate simultaneously without phase control, then power driving capacity is maximized, but power consumption peaks occur due to simultaneous actuation
Solution Approach 1:
The synchronization device pre-coordinates the switching cycles of multiple regulators by distributing phase-shifted clock signals in advance. This preliminary synchronization ensures that regulators are activated at different times, preventing simultaneous inrush currents and power consumption peaks while maintaining overall power driving capacity.
Solution Approach 2:
The system introduces asymmetric phase shifts between clock signals distributed to different integrated electronic devices. By creating intentional time offsets in the switching cycles, the system prevents simultaneous actuation of regulators, reducing peak power consumption while maintaining balanced overall power dissipation across the system.
Data Source
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Figure 3
AI summary
System including a master device (2) including: a master oscillator (21,22) generating a first clock signal (MAIN_CLK_MASTER); a master timing stage (23) which implements a master counter (99) dependent on the first clock signal and generates a first local signal (TIMEBASE_MASTER) dependent on the master counter; and a master synchronization stage (24) which generates a synchronization signal (CLKSW) synchronous with the first local signal. The system further includes a slave device (4) including: a slave oscillator (41,42) generating a second clock signal (MAIN_CLK_SLAVE) frequency-locked with the first clock signal; a slave timing stage (43) which implements a slave counter (199) dependent on the second clock signal and generates a second local signal (TIMEBASE_SLAVE) dependent on the slave counter; and a slave synchronization stage (44,45) which reads, with a timing that depends on the synchronization signal, the value of the slave counter, compares the read value with an expected value and tunes the value of the slave counter according to the outcome of the comparison.