Clock Divider Synchronization Pulse Width Scaling for SoC Power Flexibility
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Solution Overview
Problem
In complex electronic systems like SoCs, adjusting the root clock signal to accommodate different divider settings across components is challenging due to the potential impact on other components' clock dividers, leading to issues with power flexibility and synchronization at varying operating voltages.
Innovation Solution
The implementation of an electronic circuit with an oscillator, divider circuits, and a power and clock manager that dynamically scales synchronization pulse width based on divisor values, ensuring proper propagation and power management across sub-circuits, including a synchronization control circuit that adjusts divisor values and power supply voltage to maintain desired clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the root clock signal is adjusted to increase power flexibility, then power consumption can be optimized, but synchronization between different component dock dividers becomes problematic
Solution Approach 1:
A synchronization control circuit is introduced as an intermediary component that generates synchronization pulses to coordinate divisor changes across multiple dock divider circuits. This mediator ensures that when the root clock signal is adjusted, all components transition their divider settings in a synchronized manner, preventing timing conflicts while allowing power flexible operation at different clock frequencies
2Adaptability or versatility
If different component dock dividers have different divider settings, then each component can operate at optimal frequency, but changing the root dock by one component affects the divided dock of other components
Solution Approach 1:
The system employs dynamic divisor values that can be independently configured for each dock divider circuit based on component requirements. The synchronization control circuit dynamically adjusts these divisors in coordination, allowing each component to operate at its optimal frequency while maintaining system-wide synchronization through coordinated transitions
3Device complexity
If the synchronization pulse width is fixed, then circuit design is simplified, but proper propagation through divider circuits with different settings cannot be ensured
Solution Approach 1:
The synchronization pulse width is made variable rather than fixed, with its duration dynamically adjusted based on the current divisor value of the dock divider circuits. This parameter change ensures that the synchronization pulse remains valid and properly propagated through divider circuits with different settings, maintaining reliability without excessive complexity
Data Source
AI summary
An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.