Packet-Based Clock Synchronization Servo Convergence
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Solution Overview
Problem
Existing packet-based clock synchronization systems face challenges in achieving efficient convergence during startup, particularly due to network noise and baseline frequency offset of the local oscillator, which can lead to delayed or prevented synchronization.
Innovation Solution
The system employs a packet-based clock synchronization protocol that adjusts window sizes for packet selection and determines an initial frequency offset to accelerate convergence. Additionally, it uses a method with the lowest variance among various packet selection methods to improve synchronization accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a longer window duration is used for packet selection, then network noise reduction is improved, but convergence interval at startup increases
Solution Approach 1:
The patent applies dynamics by making the observation window duration variable rather than fixed. The system dynamically adjusts the window duration based on the operational phase: using shorter windows during startup/convergence phase and longer windows during steady-state operation. This resolves the contradiction by allowing the system to optimize for convergence speed initially, then switch to optimizing for noise reduction once synchronized.
Solution Approach 2:
The patent applies preliminary action by using an initial frequency offset estimate determined before正式的 synchronization begins. The system calculates an estimated frequency offset from initial packets and applies this correction in advance, which accelerates the convergence process and reduces the time needed before the longer observation window can be effectively used for noise reduction.
2Measurement precision
If baseline frequency offset of local oscillator is present, then synchronization accuracy is maintained, but convergence at startup is delayed or prevented
Solution Approach 1:
The patent applies preliminary action by determining an initial frequency offset estimate before formal synchronization begins. The system calculates this estimate from initial packets exchanged between master and subordinate clocks, then applies this correction in advance. This preliminary correction prevents the frequency offset from blocking convergence, while maintaining synchronization accuracy through the established correction mechanism.
Solution Approach 2:
The patent applies parameter changes by modifying the frequency offset parameter dynamically. The system determines an initial frequency offset estimate and uses this to adjust the subordinate clock's frequency parameter. This parameter change enables convergence by compensating for the baseline offset, while the system continues to monitor and maintain synchronization accuracy through ongoing parameter adjustments.
Data Source
AI summary
Systems and methods for packet-based network clock synchronization are provided. An integrated circuit device may include a local clock and a packet-based synchronization servo to apply a control loop to synchronize the local clock with a remote clock. The control loop may include a frequency correction to accelerate convergence.