Clock Synchronization via Timing Messages in Optical Switches
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Solution Overview
Problem
In optical communication networks, synchronization issues between the clock rates of ingress and egress cards in a telecommunications switch can lead to loss of information during signal mapping and de-mapping, particularly due to differences in clock rates between the ingress and egress cards.
Innovation Solution
A method and system that generate a reference clock to determine the first clock rate from an input signal over a specific time interval and calculate a second clock rate based on an error signal derived from the difference between the product of the first clock rate and the second time interval, ensuring synchronization between the ingress and egress cards by adjusting the second clock rate to maintain accurate timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock rates of ingress and egress cards are different to accommodate various signal rates, then signal mapping flexibility is improved, but synchronization accuracy deteriorates causing information loss
Solution Approach 1:
The patent introduces a timing message as an intermediary carrier that transports clock rate information between ingress and egress cards. This timing message acts as a mediator that enables the egress card to understand and adapt to the ingress card's clock rate, allowing flexible signal mapping while maintaining synchronization accuracy through the transmitted timing information.
Solution Approach 2:
The patent implements a feedback mechanism where the egress card receives timing messages containing clock rate information from the ingress card, compares it with its own clock rate, and adjusts its timing accordingly. This closed-loop feedback ensures that even with different clock rates, the system maintains synchronization by continuously correcting timing deviations based on the transmitted timing information.
2Adaptability or versatility
If clock rates are adjusted to match different signal protocols, then protocol compatibility is improved, but timing stability deteriorates causing jitter and drift
Solution Approach 1:
The patent applies preliminary action by pre-calculating and transmitting the required timing adjustments through timing messages before actual signal processing occurs. The ingress card determines the appropriate timing parameters in advance and embeds them in timing messages, allowing the egress card to pre-adjust its timing to maintain stability while accommodating different protocols.
Solution Approach 2:
The patent implements dynamics by making the clock rate adjustment mechanism adaptive and variable rather than fixed. The system dynamically adjusts clock rates based on the specific protocol requirements while using timing messages to maintain overall timing stability. This allows the system to be flexible with different protocols while preventing excessive jitter and drift through controlled dynamic adjustment.
3Device complexity
If simple clock rate multiplication is used for signal conversion, then device complexity is reduced, but information loss increases due to synchronization errors
Solution Approach 1:
The patent uses timing messages as an intermediary to carry precise timing information between conversion stages. Instead of relying solely on simple clock rate multiplication which causes information loss, the timing message intermediary provides additional timing context that enables more accurate signal conversion while keeping the overall device complexity manageable.
Solution Approach 2:
The patent replaces traditional mechanical or hardware-based clock synchronization mechanisms with a software/digital timing message system. This substitution allows for more precise timing control through digital processing of timing information, reducing information loss during signal conversion while maintaining relatively simple device architecture through software-based timing management.
Data Source
AI summary
A method and apparatus for timing an output signal based on timing of an input signal is provided. A method includes determining a first clock rate derived from the input signal during a first time interval measured by a reference clock. The method also includes signal processing logic to determine a second clock rate during a second time interval based on an error signal that is calculated as a difference between the first clock rate multiplied by the second time interval and a previous value of the second clock rate multiplied by the first time interval.