Clock Synchronization Circuit With Variable Divider Latency Control
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Solution Overview
Problem
Existing synchronization control circuits for SDRAMs are limited in their ability to dynamically adjust latency between internal and external clocks, leading to increased chip area and power consumption, especially at higher external clock frequencies.
Innovation Solution
A synchronization control circuit with a variable divide ratio frequency divider that adjusts the output timing of internal clocks to synchronize with external clocks, allowing for flexible latency control and reduced power consumption by cascading latch circuits and using a variable divider to divide the internal clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed divide ratio frequency divider is used, then the circuit structure is simple, but the latency between change clocks cannot be changed
Solution Approach 1:
The patent applies the dynamics principle by transforming the fixed divide ratio into a variable one. The frequency divider's divide ratio is made dynamically adjustable through control signals, allowing the circuit to adapt different latency values. This enables the same circuit structure to provide multiple latency configurations without increasing fundamental complexity.
Solution Approach 2:
The patent implements parameter changes by modifying the divide ratio parameter of the frequency divider. By changing this parameter dynamically based on control signals, the circuit can adjust latency between clocks while maintaining the same hardware structure, thus resolving the contradiction between simplicity and adaptability.
2Adaptability or versatility
If multiple delay elements are used to achieve flexible latency control, then latency adjustment capability is improved, but chip area increases
Solution Approach 1:
The patent applies universality by designing a single frequency divider circuit that can perform multiple latency control functions through variable divide ratio. Instead of requiring separate delay elements for each latency value, one multi-functional circuit handles all latency adjustments, significantly reducing chip area while maintaining flexibility.
Solution Approach 2:
By changing the divide ratio parameter of the frequency divider, the circuit achieves different latency values without adding physical delay elements. This parameter-based approach allows flexible latency control using the same hardware resources, thereby reducing the area occupied on the chip.
3Reliability
If multiple delay elements are used for synchronization, then synchronization capability is improved, but power consumption increases
Solution Approach 1:
The patent uses a single multi-functional frequency divider circuit to handle all synchronization requirements across different latency values. This eliminates the need for multiple separate delay elements, each consuming power independently. The unified circuit maintains synchronization capability while reducing total power consumption.
Solution Approach 2:
The patent achieves different synchronization delays by changing the divide ratio parameter rather than switching between multiple active delay circuits. This parameter modulation approach keeps only one circuit active at a time, reducing overall power consumption while maintaining full synchronization capability across various latency settings.
4Speed
If the external clock frequency increases, then processing speed is improved, but the need for precise latency control becomes more critical
Solution Approach 1:
The patent addresses high-speed synchronization needs by dynamically adjusting the divide ratio parameter of the frequency divider. This allows precise latency control at higher clock frequencies without requiring more complex circuitry. The parameter-based control mechanism scales well with increasing external clock frequencies.
Data Source
AI summary
A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed.