Clock Synchronization Circuit for Variable Divider Phase Matching
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Solution Overview
Problem
In semiconductor chips, as they increase in size and complexity, the physical wiring distance for clock signals can lead to phase deviations between control circuits and functional modules, causing communication issues due to variable division ratios and fixed flip-flop stages in existing clock generating circuits.
Innovation Solution
A clock generating circuit that calculates and generates delayed clocks by a predetermined maximum number of clocks from a variable divided clock, ensuring synchronization and phase matching regardless of division ratio changes, using a variable frequency division circuit and clock synchronization circuits to supply synchronized clocks to both control and functional modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the physical wiring distance of the operation clock is increased to connect control circuits and functional modules on large semiconductor chips, then the chip size and functionality are improved, but the phase deviation between clocks supplied to different modules increases causing communication failures
Solution Approach 1:
The patent segments the clock distribution system into multiple regions, with separate clock generating circuits placed in different regions of the semiconductor chip. Each clock generating circuit generates clocks for its local region, reducing the wiring distance and phase deviation within each segment while maintaining overall system functionality.
Solution Approach 2:
The patent introduces clock synchronization circuits as intermediaries between clock generating circuits and functional modules. These synchronization circuits adjust and synchronize the phases of divided clocks to match the source clock phase, acting as mediators that eliminate phase deviation caused by long wiring distances.
2Device complexity
If fixed flip-flop stages are used in clock synchronization circuits, then the circuit structure is simplified, but the phase matching between divided clocks and source clocks deteriorates when division ratio changes
Solution Approach 1:
The patent makes the clock synchronization circuit dynamic by allowing the number of flip-flop stages to be variable based on the division ratio. When the division ratio changes, the synchronization circuit adjusts the number of flip-flop stages accordingly, ensuring that the phase relationship between divided clocks and source clocks is maintained without requiring a completely redesign of the circuit structure.
Data Source
AI summary
In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules.