Clock Synchronization for Load Center Monitoring

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Solution Overview

Problem

Existing load center monitoring systems face challenges with increased complexity and size, including excessive cabling, regulatory compliance issues, and difficulties in installation and maintenance due to the 'hub and spoke' topology of individual Current Transformers (CTs) connected to a main controller.

Innovation Solution

A system utilizing a single communication bus to connect multiple smart sensor circuits to a CT concentrator, which synchronizes clocks and manages current and voltage sampling across multiple circuit branches, reducing cabling complexity and enabling efficient energy management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If individual Current Transformers (CTs) are connected to a main controller using hub and spoke topology, then current monitoring capability is achieved, but system complexity and cabling requirements increase

Engineering Contradiction:
Improvecurrent monitoring capabilityVSAvoidsystem complexity and cabling
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple individual CT monitoring functions are merged into a single integrated load center monitor device. The patent combines voltage sensing, current sensing through multiple CTs, clock synchronization, and communication capabilities into one unified controller, eliminating the need for separate CT-to-controller connections and reducing overall system complexity while maintaining monitoring reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The load center monitor is designed as a universal device that can monitor multiple circuit branches simultaneously through integrated CT connections. The single controller performs multiple functions including voltage measurement, current measurement across multiple branches, time synchronization, and data communication, replacing multiple specialized devices and reducing cabling requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If multiple smart sensor circuits are connected via a single communication bus, then cabling complexity is reduced, but clock synchronization precision becomes challenging

Engineering Contradiction:
Improvecabling complexityVSAvoidclock synchronization precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The system implements a feedback-based clock synchronization mechanism where the main controller sends time synchronization commands through the communication bus to sensor circuits, which then adjust their local clocks based on received timing information. The system accounts for transmission latency by measuring round-trip time and compensating for delays, ensuring sub-millisecond synchronization precision despite the distributed architecture

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The main controller performs preliminary time measurement and latency calculation by sending test signals to sensor circuits before actual monitoring begins. This preliminary action establishes baseline synchronization parameters and compensation values that are used during normal operation, enabling precise time synchronization to be achieved in advance before real-world variations occur

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9973036B2Automatic sub-millisecond clock synchronization
Publication Date: 2018.05.15 SCHNEIDER ELECTRIC IT CORP
  • US9973036B2 patent drawing
  • US9973036B2 patent drawing
  • US9973036B2 patent drawing

AI summary

According to one aspect, embodiments of the invention provide a system for monitoring a plurality of circuit branches coupled to an input line, the system comprising a communication bus, a controller having a primary clock with a first clock value and configured to sample voltage on the input line based on the first clock value, a plurality of sensor circuits, each sensor circuit having a secondary clock with a second clock value and configured to sample current in the at least one of the plurality of circuit branches based on the second clock value, and wherein the controller is further configured to initiate, via the communication bus, synchronization of at least one secondary clock and the primary clock, and to synchronize, via the communication bus, the at least one secondary clock and the primary clock to account for transmission latency in the communication bus.