Clock Synchronization via Reverse Signal Path

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Solution Overview

Problem

Existing distributed antenna systems face inefficiencies in clock synchronization due to the need for separate cables to connect distant clock sources and headend devices, which are often located in separate spaces due to size, weight, and power requirements.

Innovation Solution

A clock synchronization method where a reference clock is transmitted through a first path that includes a portion reverse to a second path through which a downlink signal is transmitted, allowing for clock synchronization between communication nodes without the need for direct, separate cabling between clock sources and headend devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate cable is used to connect the clock source and headend device, then clock synchronization can be achieved, but the device complexity and installation difficulty increase due to the need for additional cabling between distant locations

Engineering Contradiction:
Improveclock synchronizationVSAvoidcabling structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the clock signal transmission path with the existing downlink signal path by transmitting the reference clock through the same communication nodes and cables that carry downlink signals. This eliminates the need for separate dedicated cabling between the clock source and headend device, reducing structural complexity while maintaining synchronization reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The existing communication infrastructure is made multi-functional by using the same communication nodes and transmission paths for both downlink signal delivery and clock synchronization. This universal utilization of existing infrastructure eliminates the need for additional dedicated cabling, directly resolving the contradiction between achieving reliable synchronization and reducing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Use of energy by stationary object

If the headend device is placed in a separate space due to size and power requirements, then the headend device can operate with adequate space and power, but the need for additional cabling increases installation difficulty and reduces installation flexibility

Engineering Contradiction:
Improvepower supplyVSAvoidinstallation flexibility
Core Design Contradiction:
Use of energy by stationary objectVSEase of operation

Solution Approach 1:

The patent combines the clock synchronization function with the existing downlink signal transmission path, allowing the headend device to receive clock signals through the same communication infrastructure used for signal distribution. This eliminates the need for separate dedicated cabling, thereby improving installation flexibility while still allowing the headend device to be positioned in spaces appropriate for its power and operational requirements

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If a separate cable connection is made between distant clock source and headend device, then clock synchronization is achieved, but the loss of substance (cabling material) and installation cost increase

Engineering Contradiction:
Improveclock synchronizationVSAvoidcabling material
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent merges the clock signal transmission function into the existing downlink signal path, utilizing the same communication nodes and transmission medium already deployed for signal distribution. This eliminates the need for additional dedicated cabling material between distant locations, reducing substance loss and installation cost while maintaining reliable clock synchronization through the shared infrastructure

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12273833B2Method for clock synchronization of communication network, and the communication network using the same
Publication Date: 2025.04.08 SOLID
  • US12273833B2 patent drawing
  • US12273833B2 patent drawing
  • US12273833B2 patent drawing

AI summary

Provided are a clock synchronization method performed between communication nodes included in a communication network, the clock synchronization method comprises receiving a synchronization source signal through any one of remaining communication nodes except for an uppermost communication node included in the communication network, generating a reference clock for clock synchronization from the received synchronization source signal and transmitting the generated reference clock through a first path including at least a portion reverse to a second path through which a downlink signal is transmitted in the communication network.