Clock Synchronization in Daisy-Chain Networks Using Theoretical Residence Time
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Solution Overview
Problem
In daisy-chain network topologies, the combination of ordinary and transparent clocks for clock synchronization introduces inaccuracies during the calibration phase due to large corrections that modify the time of day, leading to unpredictable residence time computation and increased synchronization time across nodes.
Innovation Solution
A method and device that utilize a shared physical clock for both logical and time compensation clock modules, where a theoretical residence time is computed and used to optimize synchronization, reducing the need for duplicating protocol stacks and improving accuracy by using a theoretical residence time during pre-synchronization and synchronization phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ordinary and transparent clocks are combined for clock synchronization in daisy-chain topology, then clock synchronization capability is provided, but inaccuracies occur during calibration phase due to large corrections modifying time of day
Solution Approach 1:
The patent applies preliminary action by computing the theoretical residence time in advance during the calibration phase, before actual synchronization begins. This pre-computed value is then used to correct the time of day accurately without causing computation errors during the synchronization process itself.
Solution Approach 2:
The patent introduces an intermediary mechanism by using a separate theoretical residence time computation that mediates between the ordinary clock and transparent clock functions. This intermediary value allows accurate time correction without directly interfering with the residence time measurements used for synchronization.
2Productivity
If theoretical residence time is used during pre-synchronization phase, then synchronization time is reduced, but complexity of clock module increases
Solution Approach 1:
The patent merges the theoretical residence time computation functionality into the existing transparent clock module, which already performs residence time measurements. By combining these functions in a single module rather than adding separate components, the patent achieves faster synchronization without proportionally increasing overall system complexity.
Solution Approach 2:
The patent applies universality by designing the clock module to perform multiple functions: both traditional residence time measurement for synchronization and theoretical residence time computation for calibration. This multi-functional approach avoids the need for separate dedicated components for each function.
Data Source
AI summary
A method for synchronizing a logical clock in a device comprising a physical clock, an input port, and an output port, the device further comprising a logical clock and a time compensation clock sharing the physical clock, the time compensation clock making it possible to determine a residence time, comprising obtaining a theoretical residence time, during a pre-synchronization phase according to which the logical clock is not synchronized, adding a value representative of the obtained theoretical residence time to a residence time value stored in a synchronization message to be forwarded, during a synchronization phase according to which the logical clock is synchronized, obtaining a residence time and adding a value representative of the obtained residence time to a residence time value stored in a synchronization message to be forwarded, and synchronizing the logical clock as a function of a residence time value stored in a received synchronization message.