Clock-Synchronized Signal Generation for Reliable Domain Crossing
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Solution Overview
Problem
As the operating speed of semiconductor systems increases, the frequency of clock signals also rises, leading to insufficient time margins for signal processing, necessitating the generation of division clock signals with lower frequencies to ensure proper synchronization and domain crossing operations in semiconductor apparatuses.
Innovation Solution
A signal generation circuit comprising a clock division circuit, synchronization signal generation circuits, and a retiming circuit is employed to generate division clock signals with specific phase differences and pulse widths, allowing for precise synchronization and retiming of input signals to maintain signal integrity across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of clock signal is increased to improve operating speed, then productivity is improved, but time margin for signal processing becomes insufficient
Solution Approach 1:
The patent divides the high-frequency clock signal into multiple lower-frequency division clock signals (first division clock signal and second division clock signal) using a clock division circuit. This segmentation allows different stages of signal processing to operate at appropriate speeds, ensuring sufficient time margins for asynchronous delay operations while maintaining high overall system productivity through parallel processing across multiple clock domains.
2Reliability
If division clock signal is used for domain crossing operation, then reliability is improved, but device complexity increases
Solution Approach 1:
The synchronization signal generation circuit performs multiple functions: it generates synchronization signals based on division clock signals, adjusts pulse widths through on-control and off-control signals, and provides retiming capabilities. This multi-functional design improves reliability by ensuring proper synchronization across clock domains while minimizing the increase in device complexity through functional integration.
Solution Approach 2:
The circuit generates synchronization signals in advance before domain crossing operations are needed. The on-pulse generation circuit and off-pulse generation circuit prepare control signals that predetermine the timing and duration of synchronization operations, ensuring reliable domain crossing without adding complex real-time control mechanisms.
Data Source
AI summary
A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.