Clock-Synchronized LDO for Ripple Suppression
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Solution Overview
Problem
Low dropout voltage regulators (LDOs) used in clock-based circuits, such as SAR ADCs, experience output voltage ripples due to varying current demand during clock signal phases, leading to performance degradation and increased power consumption in existing solutions that attempt to suppress these ripples.
Innovation Solution
A low dropout voltage regulator with a control circuit that adjusts the current through a power transistor in response to the clock signal, increasing current during low clock phases and returning to normal during high phases, using a control circuit with a coupling capacitor and driving circuit to synchronize the control signal with the clock signal, thereby reducing ripple voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the LDO uses a larger power transistor to suppress ripples, then the ripple suppression capability is improved, but the circuit area is increased
Solution Approach 1:
The patent applies periodic action by detecting the clock signal phases and dynamically adjusting the power transistor current in synchronization with the clock signal. The control circuit increases the current during specific phases (when clock is low) and reduces it during other phases (when clock is high), creating a periodic current adjustment pattern that suppresses ripples without requiring a permanently larger transistor.
2Object-affected harmful factors
If the LDO increases current flowing through the power transistor at all time to suppress ripples, then the ripple suppression capability is improved, but the power consumption is increased
Solution Approach 1:
The control circuit implements periodic action by synchronizing current adjustment with clock signal phases. Current is increased only during phases when the load draws more current (when clock is low) and reduced during phases when load current is lower (when clock is high). This time-varying current control suppresses ripples while avoiding continuous high current flow, thereby reducing overall power consumption compared to maintaining elevated current at all times.
Solution Approach 2:
The patent applies dynamics by making the power transistor current variable rather than static. The control circuit dynamically adjusts the current based on real-time detection of clock signal phases and load current variations. This dynamic current control allows the system to optimize between ripple suppression and power consumption by adapting the current level to actual operational conditions rather than maintaining a fixed high current.
3Object-affected harmful factors
If the LDO enlarges the load capacitor to suppress ripples, then the ripple suppression capability is improved, but the circuit area is increased
Solution Approach 1:
Instead of using a continuously large capacitor, the patent employs periodic action through clock-synchronized current adjustment. The control circuit detects clock phases and actively compensates for current variations by adjusting the power transistor current in sync with the clock signal. This active periodic control achieves ripple suppression through timing-based current management rather than passive energy storage in a large capacitor, thereby reducing the required capacitor size and overall circuit area.
Data Source
AI summary
A low dropout voltage regulator, coupled to a load circuit receiving a clock signal, includes an amplifier; a power transistor comprising a control terminal, coupled to an output terminal of the amplifier; and a first terminal, coupled to a positive input terminal of the amplifier and the load circuit; and a control circuit, configured to control a current flowing through the power transistor in response to the clock signal.