Clock-Synchronized Pulse Width Circuit for Domain Crossing Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor apparatuses face challenges in synchronizing internal signals generated through asynchronous delay with a clock signal during domain crossing operations, requiring circuits that can generate signals with constant delay and pulse width, and enable/disable signals within a specific range.
Innovation Solution
A signal generation circuit comprising a synchronization circuit, a pulse width control circuit, and an output circuit that synchronizes input signals with a clock signal, generates start and end signals by delaying the synchronization signal, and enables/disables the output signal based on these signals to maintain accurate timing and pulse width during high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If internal signals are generated through asynchronous delay, then signal generation flexibility is improved, but synchronization with clock signal deteriorates
Solution Approach 1:
A domain crossing circuit is introduced as an intermediary component between the asynchronous delay circuit and the clock domain. This circuit includes a synchronization unit that receives the asynchronously delayed signal and a clock signal, and generates a synchronized output signal by aligning it with the clock signal edges, thereby resolving the synchronization issue while preserving the flexibility of asynchronous delay
Solution Approach 2:
The signal generation process is divided into separate functional modules: an asynchronous delay circuit for flexible signal generation, a domain crossing circuit for synchronization, and control units for managing different signal types. This segmentation allows each module to perform its specialized function optimally without compromising overall system performance
2Reliability
If domain crossing operation is performed to synchronize signals, then synchronization accuracy is improved, but circuit complexity increases
Solution Approach 1:
The domain crossing circuit is designed as a universal synchronization unit that can handle multiple types of signals (data signals, control signals, address signals) through a single integrated structure. The circuit uses configurable delay elements and multiplexers that can be programmed to accommodate different signal requirements, reducing the need for separate dedicated circuits for each signal type
Solution Approach 2:
The circuit employs configurable delay parameters and synchronization timing parameters that can be adjusted based on the specific signal requirements. By changing these parameters rather than redesigning the circuit structure, the system achieves high synchronization accuracy for different signal types while maintaining a relatively simple fixed circuit architecture
3Reliability
If signal delay is increased for synchronization, then synchronization accuracy is improved, but signal transmission speed deteriorates
Solution Approach 1:
The delay circuit uses dynamically adjustable delay elements whose delay amount can be configured based on the specific synchronization requirements of different signals. This dynamic configurability allows the system to apply minimal necessary delay for each signal type, achieving synchronization accuracy without imposing excessive uniform delay that would slow down overall signal transmission
Solution Approach 2:
The system performs preliminary synchronization by predicting and pre-adjusting the delay requirements for different signal types based on their characteristics. Configuration parameters are set in advance for different signal categories, allowing the circuit to achieve synchronization with minimal real-time adjustment and without adding excessive delay to the critical data path
Data Source
AI summary
A signal generation circuit includes a synchronization circuit, a pulse width control circuit, and an output circuit. The synchronization circuit synchronizes an input signal with a clock signal to generate a synchronization signal. The pulse width control circuit generates a start signal from the synchronization signal and generate an end signal by delaying the synchronization signal by a time corresponding to an off control signal in synchronization with the clock signal. The output circuit generates an output signal based on the start signal and the end signal.