Clock-Synchronized Ring Oscillator Circuits Using Standard Logic Gates
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Solution Overview
Problem
Existing solutions for synchronizing ring oscillators in integrated circuits cannot be laid out using standard digital design tools, leading to inaccuracies, instability, high power consumption, and increased costs.
Innovation Solution
Implementing synchronizable ring oscillators built with standard logic gates, including controlled logic gates with clock inputs and enable signals, connected in a ring configuration to synchronize with a clock signal, using components like differential buffers, tri-state inverters, gated D-latches, and 2:1 multiplexers, which are available in standard component libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If operational amplifiers are used in the ring oscillator to synchronize with clock signal, then the ring oscillator can be synchronized to fixed clock frequency, but the device complexity increases and it cannot be laid out by standard digital design tools
Solution Approach 1:
The patent replaces complex operational amplifiers with simple standard logic gates (inverters, NAND gates, NOR gates) that are readily available in standard component libraries. These simple gates serve as temporary substitutes for the complex op-amp synchronization mechanism, achieving the same synchronization function through basic digital logic operations rather than analog circuitry.
Solution Approach 2:
The patent substitutes the analog synchronization mechanism (operational amplifiers with continuous voltage control) with a digital logic-based synchronization system. By using standard logic gates controlled by clock signals and enable inputs, the system transitions from analog to digital domain, allowing synchronization to be achieved through discrete logic operations instead of continuous analog control.
2Reliability
If ground lines of input transistors are connected to synchronization signal wire, then the ring oscillator can be synchronized, but the manufacturing precision decreases and it cannot be laid out by standard digital design tools
Solution Approach 1:
The patent replaces the custom ground line connection method with standard logic gate components that have well-defined input and output terminals. These standard gates can be easily instantiated from component libraries with precise manufacturing specifications, eliminating the need for custom ground line routing that compromises manufacturing precision.
Solution Approach 2:
The patent changes the synchronization interface from ground line voltage manipulation to standard logic gate input signals. By using enable inputs and clock inputs on standard logic gates, the synchronization function is achieved through parameter changes in the logic gate operation rather than through physical ground line connections, ensuring compatibility with standard digital design tools and manufacturing processes.
3Loss of information
If the ring oscillator runs in free running mode for longer time, then more random entropy is generated, but the side channel leakage increases and response time decreases
Solution Approach 1:
The patent implements periodic synchronization of the ring oscillator to a fixed clock frequency during a short initialization period, then transitions to free running mode for entropy generation. This periodic synchronization ensures that the oscillator starts from a known state with predictable heat generation, limiting the free running duration to minimize side channel leakage while still generating sufficient entropy during the controlled free running period.
Solution Approach 2:
The patent performs preliminary synchronization of the ring oscillator to a fixed clock frequency before entering free running mode. This preliminary action establishes predictable startup conditions and generates a known amount of heat, ensuring stable initial operation. By completing the synchronization phase beforehand, the oscillator can then operate in free running mode for the minimum necessary time to generate required entropy, thereby reducing side channel leakage exposure.
4Reliability
If the ring oscillator uses non-standard logic gates, then synchronization performance improves, but the cost increases and behavior becomes less well understood
Solution Approach 1:
The patent designs the synchronization mechanism using universal standard logic gates (inverters, NAND gates, NOR gates) that can perform multiple functions within the ring oscillator structure. These standard gates serve both as oscillation elements and as synchronization points, eliminating the need for specialized non-standard gates. The enable inputs and clock inputs on these standard gates provide the necessary synchronization control without requiring custom components.
Solution Approach 2:
The patent replaces expensive or specialized logic gates with inexpensive standard logic gates available in every standard component library. These standard gates are well-characterized with well-understood behavior, ensuring predictable performance while reducing manufacturing cost. The simplicity of these standard gates makes them easier to manufacture and integrate compared to non-standard gates, while still achieving the required synchronization accuracy through proper circuit configuration.
Data Source
AI summary
Several ring oscillator constructions are provided. The ring oscillator includes a plurality of logic gates connected in a ring configuration. An output of each except a last of the plurality of logic gates is used as an input for a next one of the plurality of logic gates. The output of the last of the plurality of logic gates is fed back to and used as an input for a first of the plurality of logic gates. A logic gate of the plurality of logic gates includes an enable input to receive an enable signal to enable the logic gate and thereby the ring oscillator. The plurality of logic gates includes at least one controlled logic gate that also includes a clock input to receive a clock signal to control the at least one controlled logic gate and thereby synchronize the ring oscillator to the clock signal.