Clock-Synchronized Signal Generation for High-Frequency Domain Crossing
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Solution Overview
Problem
Semiconductor apparatuses face challenges in synchronizing internal signals generated through asynchronous delay with clock signals, particularly as clock frequencies increase, requiring efficient methods to manage signal delays and domain crossings to maintain operational margins.
Innovation Solution
A signal generation circuit comprising a clock divider circuit, on-pulse generation circuit, off-pulse generation circuit, and output signal generation circuit, which generate divided clock signals and delay signals in synchronization with multiple clock phases to produce output signals with predetermined pulse widths, enabling effective synchronization and domain transformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve processing speed, then productivity increases, but the difficulty of synchronizing internal signals with clock signals increases
Solution Approach 1:
The patent divides the clock signal into multiple divided clock signals (first divided clock signal, second divided clock signal, third divided clock signal, fourth divided clock signal) with different phases. This segmentation allows internal signals to be synchronized with appropriate clock phases, managing the complexity of signal timing at high clock frequencies by breaking down the single clock domain into multiple coordinated sub-domains.
2Reliability
If divided clock signals are used to maintain operational margins, then reliability improves, but device complexity increases
Solution Approach 1:
The patent employs periodic divided clock signals with specific phase relationships (90-degree phase differences between adjacent divided clock signals) to systematically manage timing margins. This periodic structure allows predictable synchronization points throughout each clock cycle, ensuring reliable operation while maintaining a regular, manageable clock signal architecture rather than arbitrary complex waveforms.
3Measurement precision
If domain crossing operations are performed to synchronize asynchronous signals, then measurement precision improves, but the number of required operations increases
Solution Approach 1:
The patent performs preliminary synchronization by generating on-pulse signals and off-pulse signals that are预先 aligned with the divided clock signals before the actual domain crossing operation. This preliminary action establishes proper timing relationships in advance, reducing the complexity and time required for subsequent synchronization operations when data actually needs to cross clock domains.
Data Source
AI summary
A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.