Clock Timing Synchronization via Dual-Link Transmission

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Solution Overview

Problem

Existing technologies face challenges in synchronizing the playback of audio content among multiple playback devices in a group, especially in environments with network congestion, latency, and other impairments.

Innovation Solution

The proposed solution involves transmitting clock timing to playback devices via two or more communications links, using a combination of primary and secondary communication protocols or links, such as wireless local area networks (WLANs) and optical or radio frequency links, to facilitate clock synchronization and synchronous playback.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If clock timing is transmitted via a single network communication link, then the system complexity is low, but the synchronization reliability deteriorates under network congestion and latency

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidcommunication link complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The communication path for clock timing transmission is segmented into multiple independent links. The system divides the single communication channel into separate WLAN and wireline (Ethernet) paths, allowing clock timing data to be transmitted through different physical mediums simultaneously, thereby improving reliability against network congestion and latency on any single link.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A dedicated clock timing communication mechanism is introduced as an intermediary between the audio source and playback devices. This intermediary layer provides specialized timing signal transmission that operates independently from the main audio data stream, ensuring that synchronization signals maintain high reliability even when general network conditions are poor.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If multiple communication links are used for clock timing transmission, then the synchronization accuracy is improved, but the device complexity increases

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidcommunication protocol complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system dynamically selects and switches between different communication links based on real-time network conditions. The clock timing transmission adapts its path by choosing between WLAN and wireline connections depending on which provides better performance at any given moment, thereby maintaining high synchronization accuracy without requiring complex permanent multi-link infrastructure.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements clock timing transmission with more redundancy than strictly necessary for basic functionality. By sending timing signals through multiple links simultaneously or having backup paths ready, the system ensures that synchronization accuracy is maintained even when some links fail or degrade, accepting the additional complexity as a trade-off for robust performance.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12277364B2Synchronization via out-of-band clock timing signaling
Publication Date: 2025.04.15 SONOS INC
  • US12277364B2 patent drawing
  • US12277364B2 patent drawing
  • US12277364B2 patent drawing

AI summary

Disclosed embodiments include facilitating clock synchronization and/or synchronous playback among multiple playback devices in a group. An individual playback device estimates and/or calculates a clock time at a clock time source (or a time offset/error between the playback device and the clock time source) based on (i) first clock timing received from the clock time source via a primary timing link and (i) second clock timing received from the clock time source via a secondary timing link. In some embodiments, estimating and/or calculating a clock time and/or clock time offset/error comprises estimating and/or calculating the clock time and/or clock time offset/error with a state estimator, such as a Kalman filter, an extended Kalman filter, or other state estimator configured to estimate a clock time and/or clock time error based on clock timing received via two or more communications links.