Shared Clock Circuit Timing Modes to Prevent Undesired Peripheral Operation
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Solution Overview
Problem
In electronic systems with shared clock signals, peripherals may operate in undesired modes or states when not communicating with the microprocessor, due to the continuous generation of clock signals, leading to inefficiencies and potential errors.
Innovation Solution
A circuit arrangement and method that allow for generating clock signals in multiple timing modes for peripherals, using a logic circuit to detect operating modes and generate locking signals to inhibit or enable peripherals, allowing for efficient communication and operation based on specific requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal is generated continuously for a particular peripheral, then the peripheral can operate reliably, but other peripherals may execute undesired operations when they should be inactive
Solution Approach 1:
The patent segments the clock signal distribution by introducing individual enable signals for each peripheral. Each peripheral receives the continuous clock signal but is controlled by its own enable signal that gates whether the peripheral actually operates on the clock cycles. This allows the clock to be continuously available while preventing undesired operations in inactive peripherals.
Solution Approach 2:
The patent introduces enable signals as intermediary control elements between the continuous clock signal and each peripheral. These enable signals act as mediators that selectively permit or block the clock signal's effect on each peripheral, allowing reliable clock generation while preventing harmful operations in inactive peripherals.
2Duration of action of stationary object
If the clock signal is generated continuously, then peripherals can operate without interruption, but communication efficiency decreases when peripherals are not actively communicating
Solution Approach 1:
The patent makes the peripheral operation dynamic by introducing enable signals that can be changed at runtime. Each peripheral can be dynamically enabled or disabled based on current communication needs, allowing the system to adapt between continuous operation mode and power-saving mode, thereby improving communication efficiency while maintaining clock continuity.
Solution Approach 2:
The patent implements periodic enabling of peripherals based on communication requirements. Instead of continuously operating all peripherals, the system periodically enables only those peripherals that need to communicate at given time intervals, improving overall system efficiency while maintaining the ability for rapid activation when needed.
3Adaptability or versatility
If chip-select mechanisms are used to select peripherals, then peripheral selection is possible, but the device complexity and pin count increase
Solution Approach 1:
The patent merges the clock signal distribution function with peripheral enable control. By using the same continuous clock signal for all peripherals and controlling operation through enable signals, the system eliminates the need for separate chip-select lines and complex selection logic, reducing device complexity while maintaining peripheral selection capability.
Solution Approach 2:
The patent makes the clock signal universal by using it for all peripherals simultaneously. The single continuous clock signal serves multiple functions: it provides timing for active peripherals and serves as a reference for inactive peripherals, which are controlled through enable signals. This multi-functional approach eliminates the need for dedicated selection mechanisms.
Data Source
AI summary
In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.